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SystemVerilog UVM VCS GDB RISCV C Assertion-based Verification Functional Coverage Random Stimulus Firmware ASIC Verification Memory Subsystem High Speed IO Object Oriented Programming +9 more Show less

Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation DevOps Synthesis CDC Digital Design Hardware Design +8 more Show less

RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting +8 more Show less

RTL Verilog SystemVerilog Python Perl SoC CDC Synthesis VCS GDB Debussy dc_shell DFT Microarchitecture Scripting Silicon Debug Physical Design +12 more Show less

SystemVerilog UVM RTL Python Perl VCS dc_shell GDB Debussy ASIC Design Pre-silicon Verification Object-Oriented Programming Scripting Design Automation Functional Coverage +10 more Show less

System Verilog UVM C++ Python Perl Formal Verification Constraint Random Verification Coverage Metrics Logic Design ASIC Verification DFT IST Object-Oriented Programming Automation +9 more Show less

SystemVerilog UVM RTL Python Perl VCS dc_shell GDB Debussy ASIC Design Pre-silicon Verification Object-Oriented Programming Design Automation Scripting Coverage-based Verification +10 more Show less

System Verilog UVM RTL Verilog Python VCS Verdi Computer Architecture Functional Coverage Scripting ASIC Verification Simulation Tools +7 more Show less

ASIC Emulation Cadence Palladium Mentor Veloce Verilog SystemVerilog VHDL C++ Python Tcl Perl AMBA AXI4 Bare Metal Embedded Firmware UVM CI/CD +10 more Show less

ASIC Emulation Cadence Palladium Mentor Veloce Verilog SystemVerilog VHDL C++ Python Tcl Perl ARM AMBA AXI4 Bare Metal Firmware UVM CI/CD RTL +12 more Show less

ASIC Package Design Substrate Interposer Bump Design PCB Design Python Perl SQL PowerBI Data Analytics Data Visualization Semiconductor Theory +8 more Show less

ASIC Package Design PCB Design Python Perl SQL PowerBI Data Analytics Data Visualization Semiconductor Theory Transmission Lines Design Verification Defect Metrics +8 more Show less

SystemVerilog UVM Ethernet NVLink CXL Python Perl Assertion-based Verification Functional Coverage ASIC Design High Speed I/O Verification Infrastructure Scripting post silicon verification +9 more Show less

ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics +12 more Show less

ASIC Physical Design Logic Synthesis Formal Verification Equivalence Checking RTL Timing Closure Clock Domain Crossing MTBF Analysis Synopsys Cadence Python TCL Perl Make EDA Tools Netlisting ECO Generation +12 more Show less

Static Timing Analysis (STA) Timing Closure Physical Design Logic Synthesis DFT Noise Analysis RTL ASIC AMS Equivalence Checking Automation +6 more Show less

ASIC DFT Scan Insertion ATPG Verilog SystemVerilog Python Bash Perl UPF Gate Level Simulation SDF RTL Physical Design Formal Verification DRC Synthesis Silicon Engineering +13 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture +9 more Show less

ASIC DFT System Verilog Tcl Python Perl JTAG Scan BIST ATPG TestMax Tetramax Tessent PrimeTime Verilog RTL Logic Equivalency Checking +12 more Show less

Digital Design FPGA Silicon Bring-up Characterization Mixed Signal Design MIPI HDMI TCON Micro-architecture Emulation Verification Validation +7 more Show less