Senior ASIC Verification Engineer

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TX
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 4 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k

This role $177k

$125k $236k

below market most similar roles pay here above market

This role pays less than 55% of similar roles. Most pay $168,500–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

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The Senior ASIC Verification Engineer joins a global team to verify global IP across multiple product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI. You will partner with design and architecture teams to make implementation choices, craft verification test plans, maintain regressions, and close coverage to sign off on functional correctness and performance. Daily responsibilities include developing verification infrastructure, automating flows for generated RTL, and building verification components using SV/UVM methodology. You must drive coverage-based verification closure and resolve issues with cross-functional teams. Required skills include pre-silicon verification experience, SystemVerilog, UVM, and ASIC design flows. You should possess programming skills in Perl or Python, along with experience using tools like dc_shell, VCS, Debussy, and GDB to solve complex hardware verification problems.

Skills

SystemVerilog UVM ASIC Verification Python Perl RTL VCS dc_shell GDB Debussy Object-Oriented Programming Design Automation Pre-silicon Verification Coverage-based Verification

What you'll do

Develop test plans, tests, and verification infrastructure for global IP across multiple products.
Define, develop, and automate flows and methodologies to verify generated RTL.
Build verification components using SV/UVM methodology.
Ensure code and functional coverage of all verified RTL.
Drive coverage-based verification closure for design sign-off.
Partner with design and architecture teams to make implementation choices and resolve verification issues.
Maintain regressions and verify both functional correctness and performance expectations.

What we're looking for

BS/MS in Electrical or Computer Engineering or equivalent experience.
5+ years of proven design verification experience.
Experience in pre-silicon verification using UVM and SystemVerilog.
Experience in ASIC design/implementation flow and design automation.
Programming and scripting experience in Perl or Python.
Exposure to design and verification tools such as dc_shell, VCS, Debussy, or GDB.
Previous experience automating tasks in the design verification process (preferred).
Hands-on experience in object-oriented programming (preferred).

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