Senior ASIC Verification Engineer

Nvidia

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TX
Salary: $136,000–$218,500 / yr
Posted: 9 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k

This role $177k

$126k most similar roles pay here $230k

This role pays less than 53% of similar roles. Most pay $168,500–$216,062 — the shaded band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

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As a Senior ASIC Verification Engineer, you will join the team to verify global IP across multiple product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI. You will partner with design and architecture teams to make implementation choices, craft and implement verification test plans, maintain regressions, and close coverage for functional correctness and performance. Your daily responsibilities include developing test plans and infrastructure, automating flows for generated RTL, and building verification components using SV/UVM methodology. To succeed, you must possess expertise in pre-silicon verification, SystemVerilog, UVM, and ASIC design flow. You will utilize tools such as VCS, dc_shell, Debussy, or GDB while utilizing Perl or Python for scripting. The role focuses on solving complex technical challenges by ensuring code and functional coverage of RTL across various hardware blocks.

Skills

SystemVerilog UVM RTL Python Perl VCS dc_shell GDB Debussy ASIC Design Pre-silicon Verification Object-Oriented Programming Scripting Design Automation Functional Coverage

What you'll do

Develop test plans and verification infrastructure for global IP across multiple product lines.
Build verification components using SystemVerilog and UVM methodologies.
Define and automate flows to efficiently build, deploy, and verify generated RTL.
Ensure full code and functional coverage of all verified RTL.
Drive coverage-based verification closure to ensure functional correctness and performance.
Identify corner cases and resolve complex verification issues in collaboration with design teams.
Maintain regressions and sign off on designs for production readiness.

What we're looking for

BS/MS in Electrical Engineering, Computer Engineering, or equivalent experience.
5+ years of proven design verification experience.
Experience in pre-silicon verification using UVM and SystemVerilog.
Knowledge of ASIC design/implementation flow and design automation.
Programming and scripting experience in Perl or Python.
Proficiency with tools such as dc_shell, VCS, Debussy, or GDB.
Strong communication and collaboration skills to work across functional teams.
Experience in object-oriented programming and automating verification tasks.

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