ASIC Technical Leader, RTL

Cisco

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CAAustin, TX
Salary: $186,900–$267,700 / yr
Employment: Full-time
Posted: 6 days ago
Freshness: Confirmed live today
Closes: Dec 18, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $227k

$153k $280k

below market most similar roles pay here above market

This role pays more than 71% of similar roles. Most pay $177,250–$233,050 — the blue band above. At the midpoint, this role pays about $227k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Technical Leader, RTL

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ASIC Technical Leader- RTL will join the Silicon One team to develop hardware platforms for switching, routing, and wireless products. Working within the Silicon One development organization, you will collaborate with front-end RTL and backend physical design teams to understand chip architecture. Your primary responsibilities include driving high-quality structural test, functional test, diagnostic feature implementation, IP development and integration, and test access for high-speed IO with protocols. You will ensure robust silicon solutions meet performance standards for scalable networking architecture. Required skills include Verilog and SystemVerilog coding, CDC/RDC concepts, and front-end tools like simulators, linting, synthesis, and formal verification. You must also possess experience with AMBA protocols, JTAG, memories, and optionally power optimization techniques, UPF, SDC constraints, DFT/MBIST, and post-silicon debug.

Skills

Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug RTL

What you'll do

Drive high-quality structural and functional test implementation for silicon solutions.
Implement diagnostic features and test access for high-speed IO with protocols.
Develop and integrate IP blocks into the chip architecture.
Ensure robust and reliable silicon performance that meets corporate standards.
Collaborate with front-end RTL and backend physical design teams to understand chip architecture.
Deliver advanced networking silicon aligned with scalable and flexible architectures.

What we're looking for

10+ years of industry experience in ASIC digital design.
Experience in Verilog/System Verilog coding.
Experience with front-end tools including Verilog simulators, linting, CDC checkers, synthesis, and formal verification.
Experience with industry standard interface protocols such as AMBA (AXI, APB, AHB), JTAG, and memories.
Experience with power optimization techniques, power intent (UPF), and power estimation (preferred).
Experience with DFT/MBIST (preferred).
Experience with post-silicon debug (preferred).

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