Senior ASIC RTL Engineer

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CAAustin, TX
Salary
$167,700–$245,200 / yr
Employment
Full-time
Posted
6 days ago
Freshness
Confirmed live today
Closes
Dec 25, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $206k
$138k $257k
below market most similar roles pay here above market

This role pays more than 60% of similar roles. Most pay $168,500–$217,500 — the blue band above. At the midpoint, this role pays about $206k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · Senior ASIC RTL Engineer

Role Posting Log in to save

The Senior ASIC RTL Engineer joins the Silicon One team to develop hardware platforms for switching, routing, and wireless products. In this role, you will collaborate with front-end RTL and backend physical design teams to understand chip architecture while driving high-quality Design for Test RTL. Your primary responsibility is ensuring robust, reliable silicon solutions that meet specific performance standards for scalable and flexible networking silicon. You will utilize Verilog and System Verilog for coding, while employing front-end tools for simulation, linting, CDC checkers, synthesis, and formal verification. Required expertise includes industry-standard interface protocols such as AMBA, JTAG, and memories. Preferred skills include power optimization techniques, power intent using UPF, power estimation, DFT/MBIST, and post-silicon debug to solve complex hardware design challenges within the networking domain.

Skills

Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug Power Optimization Power Estimation

What you'll do

  • Drive high-quality Design for Test (DFT) RTL for networking silicon.
  • Ensure robust and reliable silicon solutions meet performance and innovation standards.
  • Collaborate with Front-end RTL and backend physical design teams to understand chip architecture.
  • Develop scalable and flexible hardware architectures for Cisco Silicon One products.
  • Utilize Verilog and System Verilog for coding and front-end tool integration.
  • Implement industry standard interface protocols including AMBA, JTAG, and memories.
  • Apply power optimization techniques and power intent (UPF) during the design process.
  • Perform post-silicon debug to ensure hardware functionality.

What we're looking for

  • Bachelor's or Master's Degree in Electrical or Computer Engineering required.
  • At least 7 years of experience required.
  • Prior experience in Verilog/System Verilog coding required.
  • Prior experience with front-end tools including simulators, linting, CDC checkers, synthesis, and formal verification required.
  • Prior experience with industry standard interface protocols such as AMBA (AXI, APB, AHB), JTAG, and memories required.
  • Prior experience with power optimization techniques, power intent (UPF), and power estimation (preferred).
  • Prior experience with DFT/MBIST is a plus (preferred).
  • Prior experience with post-silicon debug (preferred).

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