ASIC Post silicon DFT Technical Leader

Cisco

Confirmed live today Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TXSan Jose, CA
Salary
$177,600–$257,400 / yr
Employment
Full-time
Posted
14 days ago
Freshness
Confirmed live today
Closes
Dec 4, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $204k
This role $218k
$154k $268k
below market most similar roles pay here above market

This role pays more than 63% of similar roles. Most pay $177,250–$231,300 — the blue band above. At the midpoint, this role pays about $218k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Post silicon DFT Technical Leader

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The ASIC Post silicon DFT Technical Leader joins the Silicon One development organization to lead the post-silicon process and quality process through the entire production phase. Working within the Silicon One team, this senior role involves collaborating with product engineering, reliability, board, package, functional test, and system teams to define post-silicon bringup to production roadmaps and drive DFT requirements early in the design cycle. Key responsibilities include crafting next-generation networking chips and managing yield, reliability, and production scalability. Required technical skills include gate level simulation using VCS, post-silicon validation, and debugging with ATE patterns and P1687. Preferred competencies include Verilog design for custom DFT logic, IP integration, DFT CAD development, test architecture, methodology, infrastructure test, and Test Static Timing Analysis.

Skills

ASIC DFT Post-Silicon Validation Verilog VCS Gate Level Simulation ATE Patterns P1687 Static Timing Analysis DFT CAD Hardware Bring-up IP Integration Test Architecture Methodology Infrastructure

What you'll do

  • Define post-silicon bring-up and production roadmaps in coordination with cross-functional engineering teams.
  • Drive DFT requirements early in the design cycle for next-generation networking chips.
  • Lead the post-silicon process and quality management through the entire production phase.
  • Perform post-silicon validation and debug using VCS, ATE patterns, and P1687.
  • Manage yield, reliability learnings, and ramp acceleration for high-volume production.
  • Develop custom DFT logic and integrate IP using Verilog design experience.
  • Oversee DFT CAD development including test architecture, methodology, and infrastructure.

What we're looking for

  • Bachelor's or Master's Degree in Electrical or Computer Engineering required.
  • At least 12 years of experience required.
  • Experience in post-silicon validation, hardware bring-up, yield/reliability learnings, ramp acceleration, FA efficiency, and production scalability required.
  • Experience working with DFT teams and post-silicon validation from initial bring-up to high volume production required.
  • Experience with Gate level simulation and debugging with VCS or other simulators required.
  • Post-silicon validation and debug experience with ATE patterns and P1687 required.
  • Verilog design experience for developing custom DFT logic and IP integration (preferred).
  • Familiarity with functional verification, DFT CAD development, test architecture, methodology, infrastructure, and test static timing analysis (preferred).

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