ASIC DFT Technical Leader

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CAAustin, TX
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
8 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k
This role $227k
$143k $281k
below market most similar roles pay here above market

This role pays more than 72% of similar roles. Most pay $177,250–$231,737 — the blue band above. At the midpoint, this role pays about $227k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC DFT Technical Leader

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As an ASIC DFT Technical Leader within the Silicon One development organization, you will join the Common Hardware Group to craft next-generation networking chips. You will collaborate with front-end RTL and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. Your daily responsibilities include leading the DFT and quality process through the implementation flow and post-silicon validation phases, including physical design signoff activities. You will utilize technologies such as Jtag protocols, Scan and BIST architectures, ATPG, and EDA tools including TestMax, Tetramax, Tessent, and PrimeTime. Required skills include Verilog design, gate-level simulation using VCS, and post-silicon debug with ATE patterns and P1687. You will also perform logic equivalency checking and validate test-timing.

Skills

DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation ATE P1687 RTL Physical Design

What you'll do

  • Drive DFT requirements early in the design cycle by working with front-end RTL and backend physical design teams.
  • Lead the DFT and quality process through the entire implementation flow.
  • Manage post-silicon validation phases and debug hardware issues.
  • Perform physical design signoff activities for next-generation networking chips.
  • Develop custom DFT logic and integrate IP using Verilog.
  • Execute test architecture, methodology, and infrastructure development.
  • Conduct gate-level simulation and debugging using VCS or other simulators.
  • Validate test-timing and perform logic equivalency checking using SystemVerilog.

What we're looking for

  • Bachelor's or Master's Degree in Electrical or Computer Engineering required.
  • At least 10 years of experience in the field.
  • Experience in DFT, test, and silicon engineering trends.
  • Experience with Jtag protocols, Scan, and BIST architectures including memory BIST and boundary scan.
  • Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime.
  • Experience with Gate level simulation and debugging using VCS or other simulators.
  • Post-silicon validation and debug experience with ATE patterns and P1687.
  • Verilog design experience for custom DFT logic and IP integration (preferred).

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