Senior ASIC DFT DV Engineer

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CAAustin, TX
Salary
$167,700–$245,200 / yr
Employment
Full-time
Posted
13 days ago
Freshness
Confirmed live today
Closes
Nov 13, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k
This role $206k
$139k $257k
below market most similar roles pay here above market

This role pays more than 59% of similar roles. Most pay $177,250–$217,500 — the blue band above. At the midpoint, this role pays about $206k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · Senior ASIC DFT DV Engineer

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The Senior ASIC DFT DV Engineer joins the Silicon One team to develop hardware platforms for switching, routing, and wireless products. This role involves thorough test planning and developing test benches to verify Design-for-Test architecture, supporting ATE screening, in-system test, debug, and diagnostics needs. The engineer will collaborate with design, design-verification, and physical design teams to integrate and validate test logic across all implementation phases and post-silicon validation flows. Key responsibilities include driving reusable test and debug methodologies for new silicon device models, including bare die and stacked die. Required technical skills include System Verilog for testbench development, DVE/Verdi for debugging, and proficiency in TCL, Python, or Perl. Preferred expertise includes UVM, JTAG protocol, scan architecture, MBIST, and boundary scan.

Skills

System Verilog UVM Python TCL Perl Verdi DVE JTAG MBIST DFT Scan Architecture Boundary Scan ATE post silicon validation

What you'll do

  • Develop test benches to verify Design-for-Test (DFT) architecture for ATE screening and in-system diagnostics.
  • Create comprehensive test plans based on complex design specifications.
  • Integrate and validate test logic across all implementation phases and post-silicon validation flows.
  • Drive reusable test and debug methodologies for new silicon device models, including bare die and stacked die.
  • Debug hardware issues efficiently using tools like DVE/Verdi.
  • Develop testbench environments using System Verilog.
  • Implement test strategies for innovative hardware platforms and silicon devices.

What we're looking for

  • Bachelor’s in Electrical Engineering with at least 7+ years of experience.
  • Master's degree with at least 4+ years of experience.
  • Prior experience in test planning based on complex design specifications.
  • Prior experience in testbench development using System Verilog.
  • Experience debugging using DVE/Verdi.
  • Experience with TCL, Python, or Perl.
  • UVM and advanced System Verilog knowledge (preferred).
  • Knowledge about JTAG protocol, scan architecture, MBIST, and boundary scan (preferred).

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