ASIC DFT Technical Leader, CDC

Cisco

Confirmed live yesterday High trust
Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$186,900–$267,700 / yr
Posted
38 days ago
Freshness
Confirmed live yesterday
Closes
Oct 2, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $227k
$138k most similar roles pay here $282k

This role pays more than 75% of similar roles. Most pay $174,600–$227,350 — the shaded band above. At the midpoint, this role pays about $227k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC DFT Technical Leader, CDC

Role Posting Log in to save

As an ASIC DFT Technical Leader - CDC within the Common Hardware Group, you will join a multi-disciplined engineering team to define, design, and verify ASIC and ASIC subsystems for various platforms. Your daily responsibilities include developing subsystems for high-volume production, meeting power, performance, and area goals, and establishing processes, methods, and tools for complex implementations. The role requires expertise in RTL development, CDC/RDC concepts, and maintaining CDC/RDC flows while signing off on constraints and waivers. You will perform analysis on synthesis optimized gate netlists regarding static glitch hazards. Preferred technical skills include SDC constraints development, VCS simulation, and SystemVerilog Assertions (SVA). This role focuses on the core hardware platforms for switching, routing, and wireless products, specifically addressing the design and qualification of silicon and hardware components in the AI era.

Skills

ASIC RTL CDC RDC SDC VCS SystemVerilog Assertions SVA Synthesis Gate Netlists

What you'll do

  • Define, design, and verify ASIC and ASIC subsystems for various Cisco platforms.
  • Meet specific power, performance, and area goals within a multi-disciplined engineering team.
  • Develop and document ASIC subsystems for high-volume production and quality standards.
  • Establish processes, methods, and tools for the implementation of complex designs.
  • Implement RTL designs while managing CDC/RDC concepts and constraints.
  • Perform analysis on synthesis optimized gate netlists to identify and resolve static glitch hazards.
  • Develop SDC constraints and perform VCS simulation using SystemVerilog Assertions (SVA).

What we're looking for

  • Candidates must have a Bachelor's degree with 8+ years of experience, a Master's with 6+ years, or a PhD with 3+ years.
  • Experience in RTL development is required.
  • Experience with CDC/RDC concepts and relevant design implementation is required.
  • Experience maintaining CDC/RDC flow and signing off on constraints and waivers is required.
  • Experience with static glitch hazards and analysis of synthesis optimized gate netlists is required.
  • SDC constraints development experience is preferred.
  • VCS simulation and SystemVerilog Assertions (SVA) experience are preferred.

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