ASIC DFT Technical Leader, CDC

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CAAustin, TXSeattle, WA
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
14 days ago
Freshness
Confirmed live today
Closes
Nov 27, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k
This role $227k
$147k $281k
below market most similar roles pay here above market

This role pays more than 73% of similar roles. Most pay $177,250–$229,100 — the blue band above. At the midpoint, this role pays about $227k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC DFT Technical Leader, CDC

Role Posting Log in to save

The ASIC DFT Technical Leader - CDC will join the Common Hardware Group to define, design, and verify ASIC and ASIC subsystems for various platforms. Working within a multi-disciplined engineering team, the successful candidate will develop subsystems for high-volume release while meeting specific power, performance, and area goals. Daily responsibilities include designing and documenting complex developments, defining processes, and maintaining CDC/RDC flows. The role requires expertise in RTL development, CDC/RDC concepts, and signing-off constraints and waivers. Candidates must perform static glitch hazard analysis on synthesis optimized gate netlists. Preferred technical skills include SDC constraints development and VCS simulation using SystemVerilog Assertions. This position addresses the technical challenge of creating innovative hardware platforms for switching, routing, and wireless products within the AI era.

Skills

ASIC RTL CDC RDC SDC VCS SVA SystemVerilog Synthesis Gate Netlists

What you'll do

  • Define, design, and verify ASIC and ASIC subsystems for various Cisco platforms.
  • Meet specific power, performance, and area goals for hardware products.
  • Design and document ASIC subsystems for high-volume production and quality release.
  • Develop and maintain CDC/RDC flows and sign-off constraints and waivers.
  • Perform static glitch hazard analysis on synthesis optimized gate netlists.
  • Define processes, methods, and tools for complex design and implementation developments.
  • Develop SDC constraints and perform VCS simulation using SystemVerilog Assertions.

What we're looking for

  • Bachelor’s degree with 8+ years of related experience, or master’s with 6+ years, or PhD with 3+ years of related experience.
  • Prior experience with RTL development skills and experiences.
  • Prior experience with CDC/RDC concepts and relevant design implementation.
  • Prior experience maintaining CDC/RDC flow and signing-off constraints and waivers.
  • Prior experience with static glitch hazards and relevant analysis on synthesis optimized gate netlists.
  • Experience on SDC constraints development (preferred).
  • Experience on VCS simulation SVA (SystemVerilog Assertions) (preferred).

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