Senior ASIC Floorplan Design Engineer

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$196,000–$310,500 / yr
Posted
82 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $253k
$131k most similar roles pay here $330k

This role pays more than 90% of similar roles. Most pay $174,843–$216,250 — the shaded band above. At the midpoint, this role pays about $253k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Floorplan Design Engineer

As a Senior ASIC Floorplan Design Engineer, you will join a multi-disciplinary team to design and implement leading SOCs, CPUs, and GPUs from the early architecture development phase through physical design. You will partner with product managers, architects, and packaging teams to craft chip floorplans that optimize cost, area, performance, and power for target markets. Your daily responsibilities include identifying and solving area, interconnect, timing, and floorplan improvement opportunities while developing AI workflows and productivity tools to enhance infrastructure for speed of execution. You will manage technical risks and collaborate on mitigation strategies. The role requires expertise in physical design methodologies, power/clock/reset distribution, DFT, place and route, and timing closure. Required skills include Python, Perl, or C++ programming, along with experience in chiplet based SOC projects and algorithm development for complex hardware systems.

What you'll do

  • Design and implement chip floorplans that optimize cost, area, performance, and power for target markets.
  • Partner with multi-disciplinary teams to develop floorplans from the early chip definition phase through physical design.
  • Identify and resolve issues related to area, interconnect, timing, and floorplan improvements.
  • Develop AI workflows and productivity tools to improve infrastructure for optimizing chip area and execution speed.
  • Identify key technical and product risks and develop mitigation strategies with engineering and management teams.
  • Drive the development of large-scale ASIC floorplans for chiplet-based SOC and CPU projects.
  • Manage multiple simultaneous projects while resolving complex technical issues across various engineering teams.

What we're looking for

  • MSEE/MSCE degree or equivalent experience in chip development.
  • 10+ years of experience in chip development.
  • Experience developing SOC, CPU, graphics, memory, and I/O sub-systems.
  • Experience with physical design methodologies including floorplan, power/clock/reset distribution, DFT, place and route, and timing closure.
  • Proficiency in Python, Perl, and/or C++ programming languages.
  • Experience with Agentic AI workflows and developing productivity tools.
  • Strong written, verbal, and technical communication skills for multi-disciplinary collaboration.
  • Experience with large scale ASIC floorplans for chiplet based SOC and/or CPU projects.

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