Senior ASIC Floorplan Design Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$196,000–$310,500 / yr
Employment
Full-time
Posted
13 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k
This role $253k
$129k $330k
below market most similar roles pay here above market

This role pays more than 94% of similar roles. Most pay $170,527–$216,250 — the blue band above. At the midpoint, this role pays about $253k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Floorplan Design Engineer

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The Senior ASIC Floorplan Design Engineer joins a global team to design and implement leading SOCs, CPUs, and GPUs. This role involves crafting chip floorplans from early architecture development through the physical design phase to optimize cost, area, performance, and power for target markets. You will partner with multi-disciplinary teams to solve area, interconnect, and timing issues while developing AI workflows and productivity tools to improve infrastructure for chip area and speed of execution. Required skills include experience with SOC, CPU, graphics, memory, and I/O sub-systems, along with physical design methodologies like DFT, place and route, and timing closure. Technical requirements include Python, Perl, and C++ programming. The work focuses on solving complex technical risks for products in consumer graphics, self-driving cars, and artificial intelligence.

Skills

Physical Design Python C++ Perl DFT Place and Route Timing Closure Power/Clock/Reset Distribution Agentic AI Chiplet Packaging Algorithm Development

What you'll do

  • Craft chip floorplans that optimize cost, area, performance, and power for target markets.
  • Drive floorplan development from the early chip definition phase through physical design.
  • Identify and solve area, interconnect, timing, and floorplan improvement opportunities.
  • Develop AI workflows and productivity tools to improve infrastructure for chip area and speed.
  • Identify key technical and product risks and develop mitigation strategies with engineering teams.
  • Manage power, clock, reset distribution, and DFT during the physical design process.
  • Drive the development of large-scale ASIC floorplans for chiplet-based SOC and CPU projects.

What we're looking for

  • MSEE/MSCE or equivalent experience with broad and deep experience in chip development.
  • 10+ years of experience.
  • Experience developing SOC, CPU, graphics, memory, and I/O sub-systems in the chip.
  • Experience with physical design methodologies, chip floorplan, power/clock/reset distribution, DFT, place and route, timing closure, and packaging.
  • Strong written, verbal, and technical communications skills to present progress and options to multi-disciplinary teams.
  • Agentic AI workflows, Python, Perl and/or C++ programming language experience.
  • Experience in driving development of large scale ASIC floorplans for chiplet based SOC and/or CPU projects (preferred).
  • Strong algorithm development and programming skills (preferred).

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