ASIC Verification Engineer

Nvidia

Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$116,000–$189,750 / yr
Posted
17 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $187k
This role $153k
$104k most similar roles pay here $231k

This role pays less than 78% of similar roles. Most pay $159,525–$214,600 — the shaded band above. At the midpoint, this role pays about $153k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · ASIC Verification Engineer

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NVIDIA seeks an ASIC Verification Engineer to join its global team dedicated to pushing the boundaries of computing technology. In this role, you will collaborate with design and architecture teams to develop verification test plans, maintain regressions, and ensure functional correctness and performance expectations for multiple product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI. Key responsibilities include crafting verification infrastructure using SystemVerilog/UVM methodology, automating flows for RTL deployment and verification, and driving coverage-based verification closure. The ideal candidate has 2+ years of design verification experience with expertise in UVM, ASIC implementation flow, and scripting languages like Perl or Python. Additionally, hands-on experience with design tools such as dc_shell and VCS, along with strong communication skills, is essential for success in this role.

Skills

SystemVerilog UVM Perl Python dc_shell VCS Debussy GDB CI/CD ASIC RTL Object-Oriented Programming

What you'll do

  • Develop comprehensive test plans and verification infrastructure for global IP across multiple products.
  • Define and automate flows for efficient deployment and verification of generated RTL code.
  • Ensure full functional coverage of all RTL being verified to meet performance expectations.
  • Build verification components using SystemVerilog/UVM methodology to drive coverage-based verification closure.
  • Collaborate with design teams to identify and resolve complex verification issues and corner cases.

What we're looking for

  • 2+ years of proven design verification experience in pre-silicon verification and ASIC implementation flow.
  • Strong background in SystemVerilog/UVM for building verification components and methodologies.
  • Proficiency in Perl or Python for scripting and automating tasks in the design verification process.
  • Experience with design tools like dc\_shell, simulation tools like VCS, and debug tools such as Debussy/GDB.
  • Hands-on experience in object-oriented programming and prior work at IP or block level.
  • Excellent communication skills to collaborate effectively within teams and across functional groups.

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