ASIC Verification Engineer

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TX
Salary: $116,000–$189,750 / yr
Employment: Full-time
Posted: 4 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k

This role $153k

$103k $238k

below market most similar roles pay here above market

This role pays less than 83% of similar roles. Most pay $162,000–$216,250 — the blue band above. At the midpoint, this role pays about $153k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · ASIC Verification Engineer

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The ASIC Verification Engineer will join the global IP team to verify hardware across multiple product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI. The role involves partnering with design and architecture teams to make implementation choices, crafting verification test plans, maintaining regressions, and closing coverage to ensure functional correctness and performance. Key responsibilities include developing verification infrastructure, automating flows for generated RTL, and building components using SV/UVM methodology. Candidates must utilize SystemVerilog, UVM, Perl, and Python while employing tools like VCS, dc_shell, Debussy, and GDB. The position requires solving complex pre-silicon verification problems, identifying corner cases, and driving coverage-based closure for global IP. This role demands strong debugging skills and experience in ASIC design and implementation flows.

Skills

SystemVerilog UVM ASIC Verification Python Perl RTL VCS dc_shell GDB Debussy Object-Oriented Programming Design Automation Pre-silicon Verification Coverage-based Verification

What you'll do

Develop test plans, tests, and verification infrastructure for global IP across multiple products.
Define, develop, and automate flows and methodologies to verify generated RTL.
Build verification components using SV/UVM methodology.
Ensure code and functional coverage of all verified RTL.
Drive coverage-based verification closure for design sign-off.
Maintain regressions and verify both functional correctness and performance expectations.
Identify corner cases and resolve verification-related issues with design teams.

What we're looking for

BS/MS in Electrical or Computer Engineering or equivalent experience.
2+ years of proven design verification experience.
Experience in pre-silicon verification using UVM and SystemVerilog.
Experience in ASIC design/implementation flow and design automation.
Programming and scripting experience in Perl or Python.
Exposure to design and verification tools such as dc_shell, VCS, Debussy, or GDB.
Previous experience automating tasks in the design verification process (preferred).
Hands-on experience in object-oriented programming (preferred).

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