ASIC Verification Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$116,000–$189,750 / yr
Posted
9 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k
This role $153k
$103k most similar roles pay here $236k

This role pays less than 81% of similar roles. Most pay $162,000–$214,000 — the shaded band above. At the midpoint, this role pays about $153k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · ASIC Verification Engineer

Role Posting Log in to save

As an ASIC Verification Engineer, you will join a team focused on verifying global IP across diverse product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI. You will partner with design and architecture teams to make implementation choices, craft test plans, maintain regressions, and close coverage for functional correctness and performance. Your daily responsibilities involve developing verification infrastructure, automating flows for generated RTL, and building components using SV/UVM methodology. To succeed, you must possess experience in pre-silicon verification, ASIC design flow, and design automation. You will utilize SystemVerilog, UVM, Perl, and Python to drive coverage-based closure. The role requires proficiency with tools such as dc_shell, VCS, Debussy, and GDB while utilizing object-oriented programming to resolve complex corner cases and ensure high-quality RTL verification across multiple integrated systems.

Skills

SystemVerilog UVM RTL Python Perl VCS dc_shell GDB Debussy ASIC Design Pre-silicon Verification Object-Oriented Programming Design Automation Scripting Coverage-based Verification

What you'll do

  • Develop test plans, tests, and verification infrastructure for global IP across multiple products.
  • Define, develop, and automate flows to build, deploy, and verify generated RTL.
  • Build verification components using SystemVerilog and UVM methodologies.
  • Ensure code and functional coverage of all verified RTL.
  • Drive coverage-based verification closure to ensure functional correctness and performance.
  • Identify corner cases and resolve verification issues in collaboration with design teams.
  • Automate tasks within the design verification process using Python or Perl scripts.

What we're looking for

  • BS/MS in Electrical Engineering, Computer Engineering, or equivalent experience.
  • 2+ years of proven design verification experience.
  • Experience in pre-silicon verification using UVM and SystemVerilog.
  • Knowledge of ASIC design/implementation flow and design automation.
  • Programming and scripting proficiency in Perl or Python.
  • Experience with design and verification tools such as dc_shell, VCS, Debussy, or GDB.
  • Strong communication and collaboration skills to interact across functional teams.
  • Ability to develop test plans, build verification components, and drive coverage-based closure.

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