Senior ASIC Design Engineer

SpaceX

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Palo Alto, CAAustin, TXIrvine, CARedmond, WA
Salary
$175,000–$280,000 / yr
Posted
2 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $228k
$135k $295k
below market most similar roles pay here above market

This role pays more than 78% of similar roles. Most pay $177,250–$227,500 — the blue band above. At the midpoint, this role pays about $228k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 796 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 555 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer

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Sr. ASIC Design Engineer (Silicon Engineering) joins the Silicon Engineering team to develop next-generation ASICs for deployment in space and global ground infrastructures. This role focuses on building chips that enable reliable connectivity for the Starlink satellite constellation. You will evaluate architectural trade-offs, define micro-architecture, and implement RTL in Verilog and System Verilog. Key responsibilities include integrating designs into the top level, delivering synthesis and timing clean designs, providing timing constraints, and participating in silicon bring-up and validation. Required skills include RTL implementation experience, knowledge of standard bus protocols like AXI and AHB, and high-speed, low-power design techniques. You will also utilize Python scripting and EDA tools, including HDL simulators and lint tools, to solve complex problems like clock domain crossings and power optimization.

What does a ASIC Design Engineer earn in California?

Median $214000 from 51 postings across 8 companies.

See salary data

Skills

Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization

What you'll do

  • Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
  • Define micro-architecture and implement RTL using Verilog or SystemVerilog.
  • Integrate designs into the top level to deliver fully verified, synthesis, and timing-clean designs.
  • Coordinate with the verification team to ensure all design aspects are thoroughly covered and verified.
  • Provide timing constraints for IPs and support the physical implementation team with synthesis and timing closure.
  • Perform formality checks and support the physical implementation process.
  • Participate in silicon bring-up and validation activities.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of experience in RTL implementation.
  • Ability to work extended hours or weekends as needed for mission critical deadlines.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Ability to solve complex problems including clock domain crossings and power optimization (preferred).
  • ASIC/SoC system integration experience (preferred).
  • Experience with embedded CPU subsystems (preferred).
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.) (preferred).

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