Senior ASIC Verification Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $177k
$125k $236k
below market most similar roles pay here above market

This role pays less than 55% of similar roles. Most pay $168,500–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

The Senior ASIC Verification Engineer joins the System-On-Chip group to work on a system-level IP responsible for measuring performance across multiple projects. The primary focus involves verifying and improving verification methodologies for the corresponding RTL design to ensure high-quality system-level IP design and robust verification at unit, sub-system, and SOC levels. Key responsibilities include designing and maintaining verification environments, developing test plans, and creating UVM components, sequences, tests, and scoreboards. The role requires launching regressions, resolving issues, and automating manual steps for builds and triage. Candidates must be proficient in SystemVerilog, UVM, and OOPS-based programming, with strong coding skills in Python. Required expertise includes RTL design in Verilog, computer architecture fundamentals, and experience with verification tools like VCS and debug tools like Verdi.

What you'll do

  • Design and maintain unit-level and sub-system verification environments.
  • Develop and execute test plans based on architecture specifications.
  • Create UVM components, sequences, tests, and scoreboards.
  • Sign off on verification efforts using high-quality code and functional coverage.
  • Launch regressions, resolve issues, and meet DV milestone targets.
  • Automate manual steps for building, regression, and triage processes.
  • Improve testbench efficiency by adopting the latest verification techniques.
  • Perform end-to-end verification of IPs to ensure high-quality delivery.

What we're looking for

  • Bachelor’s or Master’s degree in Computer or Electrical Engineering (or equivalent experience).
  • At least 3 years of relevant experience.
  • Proficiency in System Verilog, UVM, and OOPS based programming.
  • Strong coding skills in Python or other industry-standard scripting languages.
  • Strong understanding of RTL design (Verilog).
  • Good understanding of computer architecture fundamentals.
  • Familiarity with verification tools such as VCS or equivalent simulation tools.
  • Familiarity with debug tools like Verdi.

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