Senior ASIC Verification Engineer

Nvidia

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$136,000–$218,500 / yr
Posted
17 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k
This role $177k
$126k most similar roles pay here $228k

This role pays more than 53% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

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The NVIDIA System-On-Chip (SOC) group seeks an experienced ASIC Verification Engineer to join its team as a senior-level contributor. In this role, you will design and maintain unit level/sub-system verification environments, develop comprehensive test plans, create UVM components, sequences, tests, and scoreboards, and ensure high-quality code and functional coverage for sign-off. You will also automate manual steps in the build, regression, and triage processes, collaborate with cross-functional teams to achieve project goals, and continuously improve testbench efficiency using cutting-edge techniques. The ideal candidate has a strong background in System Verilog, UVM, Python scripting, RTL design (Verilog), computer architecture fundamentals, and experience with verification tools like VCS and debug tools such as Verdi. This position offers the opportunity to work on high-impact projects at scale within NVIDIA’s SOC group.

Skills

SystemVerilog UVM Python Verilog VCS Verdi OOPS CI/CD Unix/Linux

What you'll do

  • Design and maintain unit level/sub-system verification environment.
  • Develop and execute test plans based on architecture specifications.
  • Create UVM components, sequences, tests, and scoreboards for verification.
  • Ensure high-quality code and functional coverage in verification efforts.
  • Automate manual steps for launching build, regression, and triage processes.

What we're looking for

  • 3+ years of experience as an ASIC Verification Engineer or similar role.
  • Proficiency in System Verilog and UVM verification methodology.
  • Strong coding skills in Python or other scripting languages.
  • Deep understanding of RTL design (Verilog) and computer architecture.
  • Experience designing and maintaining unit/sub-system verification environments.
  • Familiarity with verification tools like VCS and debug tools such as Verdi.
  • Ability to automate manual steps for build, regression, and triage processes.

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