Senior ASIC Verification Engineer

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $136,000–$218,500 / yr
Posted: 9 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k

This role $177k

$126k most similar roles pay here $230k

This role pays less than 53% of similar roles. Most pay $168,500–$216,062 — the shaded band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Verification Engineer

Role Posting Log in to save

As a Senior ASIC Verification Engineer within the System-On-Chip group, you will work on system-level IP responsible for measuring performance across multiple projects. Your primary responsibilities involve designing and maintaining unit level and sub-system verification environments, developing test plans based on architecture specifications, and creating UVM components, sequences, tests, and scoreboards. You will be responsible for end-to-end verification of IPs, ensuring high-quality code and functional coverage while automating manual steps for builds and regressions. To succeed in this role, you must possess expertise in SystemVerilog, UVM, and OOPS based programming, along with strong coding skills in Python or other scripting languages. You should also have a solid understanding of RTL design in Verilog, computer architecture fundamentals, and experience with verification tools like VCS and debug tools such as Verdi.

Skills

System Verilog UVM RTL Verilog Python VCS Verdi Computer Architecture Functional Coverage Scripting ASIC Verification Simulation Tools

What you'll do

Design and maintain unit level and sub-system verification environments.
Develop and execute test plans based on architecture specifications to verify designs.
Create UVM components, sequences, tests, and scoreboards for the design.
Achieve sign-off through high-quality code and comprehensive functional coverage.
Launch regressions, resolve issues, and meet defined verification milestone targets.
Automate manual steps involved in building, running regressions, and triaging errors.
Improve testbench efficiency by implementing modern verification techniques.
Perform end-to-end verification of IPs to ensure high-quality delivery.

What we're looking for

Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or equivalent experience.
At least 3 years of relevant experience in ASIC verification.
Proficiency in SystemVerilog and UVM is required.
Proficiency in object-oriented programming (OOPS) based programming.
Strong coding skills in Python or other industry-standard scripting languages.
Strong understanding of RTL design using Verilog.
Good understanding of computer architecture fundamentals.
Familiarity with verification tools like VCS and debug tools like Verdi.

Save