Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Confirmed live 2 days ago High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TX
Salary: $136,000–$218,500 / yr
Posted: 38 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k

This role $177k

$125k most similar roles pay here $241k

This role pays less than 55% of similar roles. Most pay $172,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Physical Design Engineer, Netlisting

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The Senior ASIC Physical Design Engineer, Netlisting joins a dynamic team to drive the physical design of high-frequency and low-power CPUs, GPUs, and SoCs at block, cluster, and full chip levels. The role focuses on netlist-related aspects including logic synthesis, equivalence checking from RTL to tapeout, netlist quality checks, and asynchronous checking such as clock domain crossing and MTBF analysis. Responsibilities include managing timing constraints, driving timing convergence, and performing ECO generation and implementation. Candidates must possess expertise in Static Timing Analysis, hardware architecture, and RTL design for timing closure. Required technical skills include proficiency in industry-standard EDA tools and scripting languages like Perl, TCL, Make, and Python. The work involves solving complex physical design challenges for high-performance computing components while improving workflows through effective tool utilization.

Skills

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture

What you'll do

Drive physical design for high-frequency and low-power CPUs, GPUs, and SoCs at various levels of integration.
Perform logic equivalence checking and formal verification from RTL to tapeout using industry-standard tools.
Conduct asynchronous checking including clock domain crossing checks and MTBF analysis.
Manage logic synthesis processes at both the block and full-chip levels.
Drive timing convergence and manage the generation of complex timing constraints.
Generate and implement ECOs to resolve design issues during the physical design flow.
Perform full-chip or sub-chip Static Timing Analysis (STA) to ensure performance targets are met.
Develop and improve workflows and productivity through the use of scripting languages and AI tools.

What we're looking for

A BS in Electrical or Computer Engineering with 5+ years of experience is required.
An MS in Electrical or Computer Engineering with 3+ years of experience is required.
Expertise in logic equivalence checking and formal verification from RTL to tapeout using industry-standard tools is required.
Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure are required.
Experience in clock-domain-crossing checking and MTBF analysis using industry-standard or in-house tools is required.
Experience in logic synthesis at the block or full-chip level for project execution and flow development is required.
Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints management, and timing convergence is required.
Proficiency in programming and scripting languages such as Perl, TCL, Make, and Python is required.

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