Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAAustin, TX
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
11 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k
This role $177k
$125k $241k
below market most similar roles pay here above market

This role pays less than 61% of similar roles. Most pay $172,000–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Physical Design Engineer, Netlisting

Role Posting Log in to save

The Senior ASIC Physical Design Engineer, Netlisting joins a dynamic team to drive the physical design of high-frequency and low-power CPUs, GPUs, and SoCs at the block, cluster, and full-chip levels. The role focuses on netlist-related aspects including logic synthesis, equivalence checking, asynchronous checking, clock domain crossing checks, and MTBF analysis. Key responsibilities involve driving timing convergence, generating timing constraints, and performing ECO generation and implementation. Candidates must possess expertise in logic equivalence checking from RTL to tapeout, hardware architecture, and Static Timing Analysis. Required technical skills include proficiency in industry-standard EDA tools and programming languages such as Perl, TCL, Make, and Python. The work addresses complex hardware challenges involving logic synthesis and flow development for advanced computing components.

Skills

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation

What you'll do

  • Drive physical design for high-frequency and low-power CPUs, GPUs, and SoCs at various levels.
  • Perform logic equivalence checking and formal verification from RTL to tapeout.
  • Conduct asynchronous checking, including clock domain crossing checks and MTBF analysis.
  • Execute logic synthesis at the block or full-chip level.
  • Manage timing constraints, drive timing convergence, and perform Static Timing Analysis (STA).
  • Generate and implement ECOs to resolve timing and logic issues.
  • Develop and improve physical design workflows and productivity using scripting languages.

What we're looking for

  • BS in Electrical or Computer Engineering with 5+ years of experience or MS with 3+ years of experience.
  • Expertise in logic equivalence checking/FV from RTL to tapeout using industry-standard tools.
  • Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
  • Experience in clock-domain-crossing checking and MTBF analysis using industry-standard or in-house tools.
  • Background in logic synthesis at either block or full-chip level for project execution and flow development.
  • Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints management, and timing convergence.
  • Proficiency in programming and scripting languages such as Perl, TCL, Make, and Python.
  • Background in DFT timing closure for various modes (preferred).

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