Senior ASIC Timing Engineer

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TXHillsboro, ORDurham, NC
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 6 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $192k

This role $177k

$126k $233k

below market most similar roles pay here above market

This role pays less than 58% of similar roles. Most pay $168,200–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Timing Engineer

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The Senior ASIC Timing Engineer will join a dynamic team to lead timing analysis and closure processes for GPUs, CPUs, LPUs, and SoCs at the block, cluster, and full chip levels. The role involves collaborating with RTL, DFX, and Clocks teams to devise closure strategies, create timing constraints, drive power convergence, and implement ECOs. Key responsibilities include improving timing convergence flows and managing full-chip or sub-chip Static Timing Analysis. Required skills include expertise in industry standard STA tools, deep sub-micron process nodes, and physical design optimization such as synthesis, placement, routing, and logic restructuring. Candidates should possess experience in crosstalk and noise analysis, logic synthesis, equivalence checking, and DFT timing closure for various modes like scan and BIST within complex digital logic designs.

Skills

Static Timing Analysis (STA) Timing Closure Physical Design Logic Synthesis DFT RTL Noise Analysis Placement Routing Equivalence Checking Scan BIST AMS GPU LPU

What you'll do

Lead timing analysis and closure processes for GPUs, CPUs, LPUs, and SoCs at block, cluster, and full chip levels.
Create and manage timing constraints for complex integrated circuits.
Drive timing and power convergence in coordination with RTL, DFX, and Clocks teams.
Implement Engineering Change Orders (ECOs) to fix timing paths, crosstalk, and noise issues.
Improve timing convergence flows in collaboration with methodology teams.
Perform physical design optimizations including synthesis, placement, routing, and logic restructuring.
Model and converge timing for deep sub-micron process nodes.
Develop automation and methodologies for Static Timing Analysis (STA) and timing convergence.

What we're looking for

BS in Electrical or Computer Engineering with 5 years of experience in Timing and STA.
MS in Electrical or Computer Engineering with 3 years of experience in Timing and STA.
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence.
Experience in timing constraints generation and management.
Expertise in analysis and fixing of timing paths through ECOs, including crosstalk and noise analysis.
Experience in physical design and optimization including synthesis, placement, routing, and logic restructuring.
In-depth knowledge of industry standard STA and timing convergence tools.
Knowledge of deep sub-micron process nodes and experience modeling and converging timing in these nodes.
Background in domain specific STA and timing convergence for GPUs, CPUs, LPU, or SOCs (preferred).
Background in logic synthesis and equivalence checking/FV (preferred).
Understanding of DFT logic and experience with DFT timing closure for various modes (preferred).
Understanding and timing closure of digital logic/macros in AMS designs/IPs (preferred).
Experience in methodology and/or flow development as well as automation (preferred).

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