ASIC DFT Engineering Technical Leader

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CAAustin, TXSeattle, WA
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live today
Closes
Dec 22, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $227k
$141k $281k
below market most similar roles pay here above market

This role pays more than 76% of similar roles. Most pay $177,250–$227,300 — the blue band above. At the midpoint, this role pays about $227k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC DFT Engineering Technical Leader

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The ASIC DFT Engineering Technical Leader joins the Silicon One development organization to lead Design-for-Test efforts for next-generation networking chips. Working within the ASIC Implementation team, you will collaborate with front-end RTL and backend physical design teams to define DFT requirements early in the design cycle. Your daily responsibilities include driving the DFT and quality process through implementation flows, post-silicon validation, and physical design signoff activities. You will also work with ATE engineers on pattern translation and validation. Required expertise includes ATPG, EDA tools like TestMax, Tetramax, or Tessent, gate level simulation with VCS, and scan insertion. Preferred skills include Verilog for custom DFT logic, Jtag protocols, SSN Scripting, Tcl, Python/Perl, and test static timing analysis constraints development for networking hardware.

Skills

ASIC Implementation Design-for-Test ATPG Tessent TestMax Tetramax Verilog Gate Level Simulation VCS SDF Scan Insertion JTAG Tcl Python Perl Static Timing Analysis Post-Silicon Validation

What you'll do

  • Drive Design-for-Test (DFT) requirements early in the chip design cycle.
  • Lead the DFT and quality process through the entire implementation flow.
  • Manage post-silicon validation and debug phases for networking chips.
  • Perform physical design signoff activities for next-generation hardware.
  • Work with ATE engineers on pattern translation and validation.
  • Develop custom DFT logic and integrate IP using Verilog.
  • Execute gate-level simulations and debug using VCS or similar simulators.
  • Develop test static timing analysis constraints and ensure timing closure.

What we're looking for

  • Bachelor’s degree in Electrical or Computer engineering with 8+ years of experience.
  • Master’s degree in Electrical Engineering or Computer Engineering with 6+ years of experience.
  • PhD in Electrical Engineering or Computer Engineering with 3+ years of experience.
  • Prior experience with ATPG and EDA tools like TestMax, Tetramax, or Tessent.
  • Prior experience with Gate level simulation, including timing-based simulations with SDF and debugging with VCS.
  • Prior post-silicon validation and debug experience.
  • Prior experience with scan insertion.
  • Verilog design experience, familiarity with functional verification, Jtag protocols, SSN Scripting, and Tcl/Python/Perl (preferred).

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