ASIC Design Engineer, Fabric/Interconnect

Apple Inc

Confirmed live yesterday Trusted

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Work type: On-site
Location: Austin, TX
Posted: 13 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $196k

$140k $245k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $168,200–$223,000.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3544 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2734 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Fabric/Interconnect

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The ASIC Design Engineer – Fabric/Interconnect joins the hardware team to design and integrate coherent and non-coherent fabrics into subsystems or SoCs. The role involves owning all aspects of RTL development, including design, templating, scripting, and RTL generation. Key responsibilities include integrating common shared IP blocks, optimizing memories and hard macros, and collaborating with front-end synthesis, STA, power, performance, and functional verification teams to ensure timing and quality. Candidates must possess knowledge of interconnect fabrics, system memory hierarchy, and cache coherency protocols like MESI, MOESI, or directory-based coherence. Technical skills required include familiarity with front-end tools for lint, CDC, and synthesis. The work focuses on on-chip interconnect architectures, specifically NoC topologies, crossbars, and arbitration for high volume production in low power applications.

What does a ASIC Design Engineer earn?

Median $200450 from 52 postings across 8 companies.

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Skills

RTL NoC SoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Directory-based Coherence Memory Hierarchy Crossbars Arbitration Scripting Front-end Synthesis

What you'll do

Design and integrate coherent and non-coherent fabrics into subsystems or SoCs.
Own all aspects of RTL development including design, templating, scripting, and generation.
Integrate and optimize common shared IP blocks, memories, and hard macros.
Coordinate with synthesis and STA teams to ensure all block timing requirements are met.
Partner with power, performance, and functional verification teams to ensure high design quality.
Incorporate proper checks at every stage of the design process to ensure on-time delivery.

What we're looking for

Bachelor of Science degree.
Experience designing and integrating coherent and non-coherent fabrics into subsystems or SoCs.
Knowledge of on-chip interconnect architectures including NoC topologies, crossbars, and arbitration.
Ability to own all aspects of RTL development design, templating, scripting, and RTL generation.
Knowledge of cache coherency protocols and memory hierarchy (preferred).
Track record of delivering large, sophisticated designs for low power applications (preferred).
Experience working with synthesis, power, performance, and verification teams (preferred).
Familiarity with front-end tools including lint, CDC, and synthesis (preferred).