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UVM SystemVerilog constraint-random verification coverage-driven sign-off Artificial Intelligence tools NPUs image/video processing pipelines custom silicon architectures Synopsys front-end suites MIPI RTL VHDL CI/CD Git +9 more Show less

Incisive Low-Power Synopsys VCS NLP Verdi Verilog SystemVerilog UVM Python Perl C C++ UPF Makefile +7 more Show less

SystemVerilog UVM Perl Python Veloce Palladium Zebu HAPS IEV VC Formal PCIe CXL Ethernet RDMA DDR TCP +11 more Show less

AI LangChain LlamaIndex System Verilog RTL ASIC flow Verification Logic synthesis Timing analysis Computer architecture Caches Arbitration policies Interconnects +8 more Show less

SystemVerilog UVM C++ Python Perl TCL DSP QAM Formal Verification Jasper VCFormal CI/CD Git Linux +9 more Show less

X-ray CSAM TDR FIB SEM TEM IR EMMI OBIRCH SIL LSM ATE Scan/ATPG MBIST JEDEC Python MATLAB LabVIEW SolidWorks AutoCAD Excel PowerPoint +17 more Show less

ASIC FPGA RTL Synthesis Functional Verification Physical Layout Emulation Program Management Milestone Planning Risk Management Dependency Tracking Delivery Execution Silicon Engineering Hardware Systems Software Development Operations Management Cross-Functional Collaboration Technical Leadership Product Management CI/CD +15 more Show less

Keysight ADS Ansys HFSS Cadence APD SPICE Python Raptor-X MATLAB Vector Network Analysis IBIS 56G PAM4 SerDes HBM UCIe CoWoS EMIB 2.5D ASIC packaging +11 more Show less

SystemVerilog UVM Linux C++ Python Perl Veloce Palladium Zebu HAPS CI/CD Networking Dashboard_management Emulation_platforms +9 more Show less

SystemVerilog VLSI RTL HDL Physical Design Computer Architecture AI GPU Deep Learning CI/CD +4 more Show less

Python Jenkins Make Kubernetes Docker CI/CD Terraform AWS GCP Azure PostgreSQL MySQL Git GitHub Bitbucket NVIDIA_Infinity_Cluster AI_toolsets ML_DevOps EDA_tools Information_Security_methods +15 more Show less

Python Perl Make Shell_scripting AI_frameworks RTL Functional_verification Formal_verification Physical_design CI/CD EDA_tools Kubernetes Docker Terraform AWS Grafana Prometheus +12 more Show less

Verilog SystemVerilog Python Perl C++ CAD VLSI ComputerArchitecture ChipFloorplan PowerClockDistribution Packaging P&R TimingClosure +8 more Show less

Python PrimeTime Tempus Git Perforce LLMs GPT Liama Chatbots Agentic AI systems Place & route tools ASIC RTL-GDSII design flow +7 more Show less

Verilog SystemVerilog UVM SVA VCS Perl Tcl Makefiles Python LLMs Agentic AI frameworks VCS-XA Gate Level Simulation Formal Equivalence +9 more Show less

SystemVerilog UVM SystemVerilog-UVM C++ C Perl Python VHDL Verilog AMBA_Bus_Protocol Formal_Verification Assertion_Based_Formal_Verification +7 more Show less

Python Perl Linux CI/CD Jenkins Kubernetes Docker gitlab REST APIs webservers VCS Verdi Terraform PostgreSQL Redis Prometheus Grafana RAG MCP LangGraph Transformer RL GenAI +19 more Show less

Verilog Python Perl Unix/Linux Makefiles CI/CD +1 more Show less

TCL Perl Python Cadence_Innovus Synopsys_ICC2 Synopsys_Design_Complier Synopsys_Formality Cadence_Logic_Equivalence_Checker Tempus Synopsys_ICV Mentor_Calibre Static_Timing_Analysis Hierarchical_floor_planning Clock_and_power_distribution Global_signal_and_I_O_planning Physical_verification_DRC/LVS Block_level_EMIR_closure ECO_strategies RTL_to_GDSII_implementation +14 more Show less

SystemVerilog UVM C++ Python PCIe CXL CHI VCS Debussy GDB +5 more Show less