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SystemVerilog UVM VCS GDB RISCV C Assertion-based Verification Functional Coverage Random Stimulus Firmware ASIC Verification Memory Subsystem High Speed IO Object Oriented Programming +9 more Show less

RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII +14 more Show less

Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation DevOps Synthesis CDC Digital Design Hardware Design +8 more Show less

DFT JTAG SCAN BIST RTL ASIC FinFET Synopsys Design Compiler Tetramax Spyglass VCS ATE Python SQL JMP Statistical Process Control ISO 9001 Root Cause Analysis +14 more Show less

System Verilog UVM ASIC Verification Python Perl C C++ Emulation Formal Verification SoC Architecture Silicon Bring-up Post-Silicon Debug +7 more Show less

Verilog System Verilog DFT ATPG RTL Design UVM OVM Python Tcl Perl Shell Synopsys DC Compiler PrimeTime Cadence Virtuoso VCS Static Timing Analysis FPGA HBM PCIe SerDes +15 more Show less

ASIC System Verilog UVM Veloce Palladium Zebu HAPS C C++ Python Perl Linux Networking Post-silicon Lab Bring-up Verification Methodology Silicon One +11 more Show less

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Power Optimization Fuse Controller Verification Synthesis +10 more Show less

ASIC FPGA RTL Verilog SystemVerilog VHDL EDA Tools Physical Design Timing Closure Power Optimization DFT Silicon Validation Device Drivers Low-level Software AI/ML Accelerators +10 more Show less

ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture +11 more Show less

RTL Design ASIC FPGA Microarchitecture Synthesis Static Timing Analysis Clock Domain Crossing CDC Tape-out FinFET EDA Tools JIRA Power Analysis Bus Fabric Formal Verification Physical Verification Microsoft Office +12 more Show less

ATE Teradyne UltraFLEX Advantest Python RF Digital Signal Generators Spectrum Analyzers VNAs Power Meters JMP Spotfire Excel Wafer Sort Final Test Root Cause Analysis RFFE Beamforming Phased Array +14 more Show less

RTL Design AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification ASIC Design +6 more Show less

RTL AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification ASIC Design +6 more Show less

SystemVerilog UVM C C++ Python Perl ASIC Verification Constrained Random Testing Assertion-based Verification VCS IES GDB Debussy Memory Management Computer Architecture Functional Coverage Scoreboards +12 more Show less

RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting +8 more Show less

System Verilog UVM C++ Python Perl Formal Verification Constraint Random Verification Logic Design Coverage Metrics Object-Oriented Programming Automation Scripting ASIC Design Verification +8 more Show less

ASIC Design RTL Design SoC Integration Logic Synthesis Timing Analysis Python Perl C++ UCIe Digital Design Verification Methodology Memory Controllers DMA Boot Controllers Fuse Controllers +10 more Show less

RTL Verilog SystemVerilog Python Perl SoC CDC Synthesis VCS GDB Debussy dc_shell DFT Microarchitecture Scripting Silicon Debug Physical Design +12 more Show less

SystemVerilog UVM RTL Python Perl VCS dc_shell GDB Debussy ASIC Design Pre-silicon Verification Object-Oriented Programming Scripting Design Automation Functional Coverage +10 more Show less