ASIC Design Engineer - Clocks IP

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAAustin, TX
Salary
$116,000–$189,750 / yr
Employment
Full-time
Posted
8 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k
This role $153k
$102k most similar roles pay here $244k

This role pays less than 88% of similar roles. Most pay $168,200–$218,000 — the shaded band above. At the midpoint, this role pays about $153k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 893 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 871 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer - Clocks IP

Role Posting Log in to save

ASIC Design Engineer – Clocks IP will join the clocks group to architect clock domains for GPU and CPU designs while satisfying functional, physical, and testing requirements. The role involves collaborating with front-end, floor-planning, back-end, software, and silicon solution teams to manage architectural constraints, improve Power, Performance, and Area (PPA), and implement new clocking topologies in RTL. You will participate in the full ASIC execution cycle, from micro-architecture and design implementation to sign-off checks and silicon bringup. Required skills include Verilog for RTL design, logic synthesis, and verification, along with proficiency in Python or other scripting languages. Candidates should possess a deep understanding of logic optimization, PPA trade-offs, and sub-micron silicon issues like noise and cross-talk. The work focuses on solving complex clocking challenges to support high-speed performance within advanced processor architectures.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 8 companies.

See salary data

Skills

ASIC RTL Design Verilog Python Clocking Networks Logic Synthesis DFT Silicon Debug Timing Closure floor-planning SOC Scripting

What you'll do

  • Architect clock domains to satisfy functional, physical, and testing design requirements for GPUs and CPUs.
  • Implement new clocking topologies in RTL while optimizing Power, Performance, and Area (PPA).
  • Develop solutions with the physical design team to support high-speed clocking and timing closure.
  • Provide clock RTL information to verification, timing, and DFT teams.
  • Participate in the full ASIC execution cycle from micro-architecture and implementation to silicon bringup.
  • Triage silicon and programming bugs in the lab alongside the silicon solution team.
  • Define efficient clock programming sequences for the software team based on the hardware programming model.

What we're looking for

  • BS in Electrical Engineering or equivalent experience (MS preferred).
  • 2+ years of relevant work experience.
  • Deep understanding of logic optimization techniques and PPA trade-offs.
  • Experience in RTL design (Verilog), verification, and logic synthesis.
  • Strong coding skills in Python or other industry-standard scripting languages.
  • Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects (preferred).
  • Implementing on-chip clocking networks (bonus).
  • Experience with clocks controller, clocks logic design, scalable designs, and hands-on silicon debug (preferred).

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