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Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Cache Hierarchy TLB Branch Prediction +12 more Show less

CPU Physical Design DTCO Synthesis Place-and-Route Static Timing Analysis PPA Python Tcl Perl timing-closure Silicon Design AI Tools Hardware Design Pathfinding +9 more Show less

SystemVerilog UVM C++ Verilog VHDL Python Perl Ruby x86 RTL Digital Design Processor Architecture Scripting Clock Gating +9 more Show less

CPU Architecture RTL Physical Design VLSI Circuit Design Power Delivery Power Gating Thermal Throttling Advanced Packaging SoC Design Process Technology High-Frequency Design Power Management +8 more Show less

Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Static Timing Analysis Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Timing Closure +11 more Show less

Tcl Python Cadence Innovus Place-and-Route Physical Design Timing Analysis Physical Verification Digital Design Automation PPA 5nm Hardware Engineering +7 more Show less

RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution +7 more Show less

SRAM Design Verilog Schematic Capture Circuit Simulation Static Timing Analysis Monte Carlo Analysis Layout Design DFT BIST NanoTime Ansys EMIR ESP-CV Liberate FinFET Nanosheet Functional Verification Power Analysis Electrical Characterization +13 more Show less

RTL Design x86 Computer Architecture Processor Pipeline Memory Hierarchy Instruction Set Architecture Logic Design Python Ruby Perl Silicon Development Lifecycle Tapeout Scripting Automation +9 more Show less

VLSI RTL Design Verilog HDL Cache Architecture CPU Coherency NoC SoC Scripting Microarchitecture Timing Closure Design for Test Physical Design Routing Fabric +8 more Show less

STA TCL Python Perl PrimeTime Tempus ICC2 Innovus RTL GDS Spice ASIC CTS AOCV POCV Signal Integrity Layout Parasitic Extraction +12 more Show less

CPU) design Verilog RTL Synthesis Place and Route GDS Logic Design Power Analysis Tapeout Microarchitecture Physical Design +6 more Show less

STA TCL Python Perl PrimeTime Tempus ICC2 Innovus RTL GDS Spice ASIC CTS AOCV POCV Signal Integrity Layout Parasitic Extraction +12 more Show less

Physical Design SPICE RTL Circuit Design PLL Jitter Analysis Standard Cell Optimization RC Delay Device Physics Hardware Engineering Electrical Engineering +6 more Show less

ASIC SoC Physical Design RTL-to-GDSII Synthesis Place & Route STA Signoff Timing Closure Power Optimization TCL Python Synopsys Cadence PPA EM/IR Power Integrity +11 more Show less

SOC Design RTL Design Verilog System Verilog UVM Design Automation Python Perl Synthesis Physical Design DFT Chip Build and Assembly Front-end Design Quality Checks +8 more Show less

Verilog SystemVerilog C++ C RTL Design Microarchitecture Power Management Clock Domain Crossing CDC Analysis Firmware DVFS Silicon Validation Design-for-Debug Design-for-Test Digital Design +10 more Show less

C C++ Python Verilog SystemVerilog Perl Matlab Vulkan UVM RTL ASIC SoC DSP LTE 5G Wi-Fi Linux Windows Machine Learning +14 more Show less

RTL Design Microarchitecture Verilog VHDL Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution +6 more Show less

SystemVerilog C C++ Python RTL Computer Architecture Assembly Regression Frameworks Waveform Analysis Verification Methodology +5 more Show less