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CPU Design Micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Simulation Emulation Formal Verification Silicon Validation Computer Architecture Physical Design +12 more Show less

STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction ASIC Back-end Design CTS POCV AOCV +12 more Show less

RTL Verilog VHDL Python Perl Microarchitecture Logic Design Functional Verification Waveform Debugging Instruction Fetch Branch Prediction +6 more Show less

SoC Design RTL Verilog System Verilog UVM Python Perl Synthesis Physical Design Design Automation DFT CAD Scripting +8 more Show less

STA PrimeTime Tempus TCL Python Perl ICC2 Innovus RTL GDS Spice Signal Integrity Layout Parasitic Extraction Physical Design Timing Closure +10 more Show less

RTL Design Microarchitecture Verilog VHDL Python Perl Logic Design Waveform Debugging Simulators Instruction Fetch and Decode Branch Prediction Out-of-Order Execution +7 more Show less

RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution +8 more Show less

SRAM Circuit Simulation Monte Carlo Analysis Static Timing Analysis Verilog BIST DFT NanoTime Ansys EMIR ESP-CV Liberate Schematic Capture Layout Design Functional Verification FinFET Nanosheet +11 more Show less

SRAM Register File Verilog Circuit Simulation Monte Carlo Analysis Static Timing Analysis FinFET Nanosheet BIST DFT NanoTime Ansys EMIR ESP-CV Liberate Schematic Capture Layout Design Functional Verification +12 more Show less

Physical Design Cadence Innovus Tcl Python Place-and-Route Timing Analysis Physical Verification Digital Design Automation Micro-architecture Logic Design +6 more Show less

Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Timing Closure Python Tcl DFT Power Management Post-silicon Debug Place-and-Route +10 more Show less

SPICE RTL Physical Design PLL Standard Cell Optimization Jitter Analysis Circuit Design Verification Hardware Engineering +4 more Show less

Synthesis Place and Route STA TCL Python Perl CSS HTML CGI Data Analytics CPU Design Automation +7 more Show less

STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction Timing Closure CTS POCV AOCV +12 more Show less

Verilog RTL Design Physical Design Synthesis Place and Route CPU Microarchitecture Logic Design Power Analysis Tapeout Flow +4 more Show less

Physical Design SPICE RTL Standard Cell Optimization PLL Circuit Design Verification Jitter Measurement Hardware Engineering +4 more Show less

ASIC SoC Physical Design RTL-to-GDSII Synthesis Place & Route STA Timing Closure Power Optimization TCL Python Synopsys Cadence PPA EM/IR Advanced Nodes +10 more Show less

Physical Design PnR STA Synthesis Python TCL Perl Machine Learning Digital Circuits Logic Design Deep Sub-micron Technology +6 more Show less

Physical Design STA Synthesis PnR TCL Python Perl Machine Learning Digital Circuits Logic Design Deep Sub-micron Technology +6 more Show less

CPU Design Micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Simulation Emulation Formal Verification Silicon Validation Physical Design +11 more Show less