CPU Physical Design Engineer, San Diego

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$122,500–$183,700 / yr
Posted
3 days ago
Closes
Dec 14, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $194k
This role $153k
$108k most similar roles pay here $255k

This role pays less than 80% of similar roles. Most pay $165,250–$223,700 — the shaded band above. At the midpoint, this role pays about $153k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 763 open roles on FindRole.

Listed pay typically runs $151,900–$229,800 across 453 roles with salary data.

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At a glance

TL;DR · CPU Physical Design Engineer, San Diego

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As a CPU Physical Design Engineer at Qualcomm Technologies, Inc., you will collaborate closely with the microarchitecture and RTL design teams to implement designs that meet stringent power, area, and performance targets using industry-standard tools and flows. Your responsibilities include conducting feasibility studies to validate design specifications, synthesizing Verilog RTL into gate-level designs, performing optimizations throughout various stages from RTL to GDS, and ensuring functional and electrical robustness of the final product. You will need a strong understanding of CPU microarchitecture, deep submicron process technology nodes, library cells, and industry-standard tools for synthesis, place & route, and tapeout flows. Additionally, experience with high-performance and low-power implementation methods is essential as you work on cutting-edge semiconductor products at scale.

Skills

Verilog RTL Synthesis Place & Route Timing Analysis Power Analysis GDS Library Cells High Performance Design Low Power Design Tapeout Flows

What you'll do

  • Work with microarchitecture team to understand specifications and design trade-offs.
  • Perform feasibility studies to validate area, timing, and power constraints.
  • Synthesize Verilog RTL into gate-level designs and optimize for performance.
  • Execute SynthPlace & Route using industry-standard tools to deliver GDS files.
  • Optimize designs from RTL to GDS to meet strict timing, power, and area goals.

What we're looking for

  • Experience in deep submicron process technology nodes.
  • Solid understanding of industry standard tools for synthesis, place & route, and tapeout flows.
  • Knowledge of CPU microarchitecture and high performance/low power implementation methods.
  • Ability to optimize designs from RTL to GDS for timing, power, and area goals.
  • Perform feasibility studies and validate implementability, area, timing, and power.

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