CPU Physical Design Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $122,500–$183,700 / yr
Posted: 86 days ago
Freshness: Confirmed live yesterday
Closes: Dec 14, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k

This role $153k

$108k most similar roles pay here $253k

This role pays less than 86% of similar roles. Most pay $172,000–$224,025 — the shaded band above. At the midpoint, this role pays about $153k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU Physical Design Engineer

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The CPU Physical Design Engineer joins the CPU Engineering team to lead innovative Central Processing Unit design efforts for multi-core operations. Working closely with microarchitecture and RTL design teams, the engineer is responsible for implementing designs that meet aggressive power, area, and performance goals. Day-to-day responsibilities include performing feasibility studies to validate implementability, synthesizing Verilog RTL into gate-level designs, and executing SynthPlace and Route processes using industry standard tools to deliver GDS. The role requires optimizing designs from RTL through GDS while ensuring functional and electrical robustness. Key technical requirements include experience with deep submicron process technology nodes, library cells, and signoff timing and power analysis. The position focuses on the specific challenge of high-performance and low-power implementation for complex CPU microarchitecture and logic design within a hardware engineering context.

Skills

Verilog RTL Design Physical Design Synthesis Place and Route CPU Microarchitecture Logic Design Power Analysis Tapeout Flow

What you'll do

Collaborate with microarchitecture teams to understand specifications and design trade-offs for pipeline and structure sizing.
Perform feasibility studies to validate implementability, area, timing, and power requirements.
Synthesize Verilog RTL into gate-level designs and perform necessary optimizations.
Execute SynthPlace and Route processes using industry standard tools to deliver GDS files.
Optimize designs from RTL through GDS to meet aggressive power, area, and performance goals.
Validate designs for both functional and electrical robustness.

What we're looking for

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 2+ years of experience in engineering.
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 1+ year of experience.
PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Knowledge of CPU microarchitecture and logic design.
Experience in deep submicron process technology nodes.
Proficiency in industry standard tools for synthesis, place and route, and tapeout flows.
Ability to perform signoff timing, power analysis, and gate level optimizations.
Knowledge of high performance and low power implementation methods.

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