below marketmost similar roles pay hereabove market
This role pays less than
84%
of similar roles. Most pay
$167,191–$227,500
— the blue band above.
At the midpoint, this role pays about
$162k
versus about
$197k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
The CPU Physical Design Engineer joins the CPU Engineering group to lead innovative Central Processing Unit design efforts. Working closely with microarchitecture and RTL design teams, the engineer implements multi-core CPU operations while meeting aggressive power, area, and performance goals. Daily responsibilities include performing feasibility studies to validate implementability, synthesizing Verilog RTL into gate-level designs, and performing SynthPlace and Route operations to deliver GDS. The role requires optimizing designs from RTL to GDS and validating functional and electrical robustness. Key technical requirements include proficiency with industry-standard tools for synthesis, place and route, and signoff timing and power analysis. Candidates should possess knowledge of CPU microarchitecture, logic design, circuits, library cells, and deep submicron process technology nodes to solve complex hardware implementation problems.
Work with the microarchitecture team to understand specifications and design trade-offs for pipeline and structure sizing.
Perform feasibility studies to validate implementability, area, timing, and power requirements.
Synthesize Verilog RTL into gate-level designs and perform necessary optimizations.
Execute SynthPlace and Route operations using industry-standard tools to deliver GDS.
Optimize designs from RTL to GDS to meet specific timing, power, and area goals.
Validate designs for functional and electrical robustness.
What we're looking for
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant engineering work experience.
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of relevant engineering work experience.
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Experience synthesizing Verilog RTL into gate level designs and performing optimizations.
Experience performing SynthPlace and Route on designs using industry standard tools to deliver GDS.
Knowledge of CPU microarchitecture (preferred).
Experience in deep submicron process technology nodes (preferred).
Knowledge of library cells, optimizations, and high performance/low power implementation methods (preferred).