Senior Staff Principal CPU SRAM Design Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$179,000–$268,400 / yr
Posted
43 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 26, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $224k
$152k most similar roles pay here $281k

This role pays more than 68% of similar roles. Most pay $177,250–$227,500 — the shaded band above. At the midpoint, this role pays about $224k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Senior Staff Principal CPU SRAM Design Engineer

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The CPU SRAM Design Engineer - Sr Staff / Principal joins the high performance CPU team as a memory designer focused on creating designs that improve performance, energy efficiency, and scalability. This individual will have full ownership of custom SRAM and RF designs from schematic capture through analysis and model generation. Daily responsibilities include developing custom digital circuits for high-speed and low-power designs, performing layout planning, functional verification, simulation, margin verification, and timing characterization. The role requires expertise in circuit simulation, Monte Carlo analysis, static timing analysis, and memory logical models using Verilog. Candidates should be proficient with tools such as NanoTime, Ansys EMIR analysis, ESP-CV, and Liberate power analysis. The work involves solving complex PPA challenges for memory components while managing the full lifecycle of design entry, layout guidance, and electrical characterization.

Skills

SRAM Circuit Simulation Monte Carlo Analysis Static Timing Analysis Verilog BIST DFT NanoTime Ansys EMIR ESP-CV Liberate Schematic Capture Layout Design Functional Verification FinFET Nanosheet

What you'll do

  • Design custom digital circuits for high-speed and low-power SRAM designs.
  • Perform schematic capture and oversee layout planning for memory components.
  • Execute functional verification and simulation to ensure circuit reliability.
  • Conduct timing characterization and margin verification for memory designs.
  • Generate deliverable collateral models through comprehensive analysis steps.
  • Collaborate with the Physical Design team to resolve memory PPA challenges.
  • Contribute to modeling, DFT features, and analysis flow development.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 12+ years of practical experience for candidates with a Bachelor's degree.
  • 10+ years of practical experience for candidates with a Master's degree.
  • 4+ years of relevant engineering experience for candidates with a PhD.
  • Experience designing SRAM circuits and using industry standard custom design tools and flows.
  • Experience with circuit simulation, Monte Carlo analysis, and static timing analysis.

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