Senior Staff Principal CPU SRAM Design Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$186,700–$280,100 / yr
Posted
25 days ago
Freshness
Confirmed live today
Closes
Mar 31, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k
This role $233k
$152k $294k
below market most similar roles pay here above market

This role pays more than 75% of similar roles. Most pay $178,413–$233,800 — the blue band above. At the midpoint, this role pays about $233k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Senior Staff Principal CPU SRAM Design Engineer

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The CPU SRAM Design Engineer - Sr Staff / Principal joins the high performance CPU team to design, improve, and analyze digital circuits for memories. This role involves full ownership of custom SRAM and RF designs from schematic capture through analysis and model generation. Key responsibilities include developing custom digital circuits for high-speed and low-power designs, performing layout planning, functional verification, timing characterization, and margin verification. The candidate must utilize industry standard custom design tools, including NanoTime, Ansys EMIR analysis, ESP-CV, and Liberate. Required skills include circuit simulation, monte carlo analysis, static timing analysis, and Verilog for memory logical models. The work focuses on solving performance, energy efficiency, and scalability challenges within semiconductor device fundamentals, specifically involving FinFet and Nanosheet technology nodes.

Skills

SRAM Design Verilog Schematic Capture Circuit Simulation Static Timing Analysis Monte Carlo Analysis Layout Design DFT BIST NanoTime Ansys EMIR ESP-CV Liberate FinFET Nanosheet Functional Verification Power Analysis Electrical Characterization

What you'll do

  • Develop custom digital circuits for high-speed and low-power SRAM designs.
  • Perform schematic capture and layout planning for custom memory designs.
  • Execute functional verification and simulation for circuit margin verification.
  • Conduct timing characterization and electrical analysis for memory components.
  • Generate deliverable collateral models through comprehensive analysis steps.
  • Coordinate with CAD teams to ensure efficient model generation.
  • Resolve memory PPA challenges in collaboration with the Physical Design team.
  • Contribute to modeling, DFT, and analysis flow development.

What we're looking for

  • BA/BS in Electrical Engineering with 12+ years of practical experience.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of relevant work experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of relevant work experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant work experience.
  • Experience designing SRAM circuits using industry standard custom design tools and flows.
  • Experience with circuit simulation, monte carlo analysis, and static timing analysis.
  • MS degree in Electrical Engineering with 10+ years of practical experience (preferred).
  • Strong knowledge of SRAM/Register File techniques, semiconductor device fundamentals, and high-performance/low-power design features (preferred).

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