CPU Microarchitecture & Cache RTL Design Engineer

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Fort Collins, CO
Salary
$144,800–$217,200 / yr
Posted
10 days ago
Freshness
Confirmed live yesterday
Closes
Sep 23, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $213k
This role $181k
$129k most similar roles pay here $294k

This role pays less than 70% of similar roles. Most pay $175,875–$250,000 — the shaded band above. At the midpoint, this role pays about $181k versus about $213k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 498 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 498 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · CPU Microarchitecture & Cache RTL Design Engineer

Role Posting Log in to save

As a senior technical contributor in the Cores Organization, the CPU Microarchitecture & Cache RTL Design Engineer will design and implement high-performance, energy-efficient cache and fabric solutions. The role involves collaborating with architects to document and execute optimized routing fabric designs while working with physical design, verification, and test teams to ensure designs are manufacturable and meet timing closure. The engineer will solve complex architectural interactions between IP and SoC designs, simplify design complexity through innovation, and mentor other engineers. Key technical requirements include experience in cache architecture development, including controller and array RTL implementation, as well as expertise in CPU coherency, coherent NoC, and replacement policies. Candidates must possess skills in Digital RTL Design, Verilog HDL, and scripting to develop the next generation of core and cache technologies for server, client, and gaming products.

Skills

RTL Design Verilog HDL Cache Architecture CPU Coherency NoC SoC Scripting Microarchitecture Timing Closure Physical Design VLSI

What you'll do

  • Design, document, and execute optimized high-performance Cache and Routing Fabric designs.
  • Develop RTL optimized for physical implementation and timing closure in coordination with Physical Design teams.
  • Create architectures and features that are clearly documented and verifiable for Design Verification teams.
  • Develop RTL that is reliable, testable, and manufacturable for Design for Test teams.
  • Resolve complex architectural interactions between IP and SoC designs across global teams.
  • Improve CPU designs by increasing quality and simplifying design complexity through technical innovation.
  • Solve complex design and tool challenges while creating technical presentations for peers and management.
  • Guide and mentor other engineers to support the development of team capabilities.

What we're looking for

  • Bachelor's or master's degree in computer engineering, Electrical Engineering, or a related technical field.
  • Experience designing and implementing high-performance, energy-efficient cache and fabric solutions.
  • Strong analytical, problem-solving, and communication skills to solve complex technical challenges.
  • Ability to mentor other engineers and share technical expertise.
  • Prior experience with Cache architecture development, including Cache Controller and Array RTL implementation (preferred).
  • Prior experience with CPU Coherency, Coherent NoC, Cache Allocation/Replacement Policy, QoS, Fairness, and Forward Progress (preferred).
  • Prior experience with Digital RTL Design, Verilog HDL, and scripting (preferred).
  • Prior experience collaborating effectively with diverse teams across disciplines (preferred).

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