Next Gen CPU Power Management RTL Design Engineer

Amd

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $166,400–$249,600 / yr
Posted: 15 days ago
Freshness: Confirmed live yesterday
Closes: Sep 18, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $210k

This role $208k

$140k most similar roles pay here $281k

This role pays less than 58% of similar roles. Most pay $177,250–$243,600 — the shaded band above. At the midpoint, this role pays about $208k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 498 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 498 roles with salary data.

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At a glance

TL;DR · Next Gen CPU Power Management RTL Design Engineer

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Next Gen CPU Power Management RTL Design Engineer will join the CPU engineering team to shape power management technologies for next-generation Ryzen, Threadripper, and EPYC processors. The role involves defining and developing microarchitecture solutions for processor clocking, reset, and power management IP while collaborating with architecture, verification, physical design, and firmware teams. Key responsibilities include authoring specifications, developing high-quality RTL, and contributing to firmware development for initialization and control flows. The candidate will utilize Verilog, SystemVerilog, and C/C++ to solve complex hardware and firmware challenges across the full product lifecycle. Required expertise includes digital design fundamentals like clock domain crossing, power-aware techniques such as DVFS and gating, and experience with silicon validation. This role addresses critical architectural decisions regarding performance, power, area, and quality for advanced SoCs and processor architectures.

Skills

Verilog SystemVerilog C C++ RTL Design Microarchitecture Power Management Clock Domain Crossing DVFS Firmware Silicon Validation Lint CDC Analysis Digital Design Low-power Design

What you'll do

Define and develop microarchitecture solutions for processor clocking, reset, and power management IP.
Author microarchitecture specifications, interface definitions, and supporting technical documentation.
Develop high-quality RTL using Verilog or SystemVerilog for next-generation CPU features.
Contribute to firmware development in C/C++ for initialization, configuration, and control flows.
Drive design quality through linting, CDC analysis, verification planning, and design review activities.
Support silicon validation, debugging, and product bring-up activities.
Identify opportunities for continuous improvement across design methodologies and workflows.

What we're looking for

Develop microarchitecture solutions and high-quality RTL using Verilog/SystemVerilog for processor clocking, reset, and power management IP.
Contribute to firmware development in C/C++ for initialization, configuration, and control flows.
Drive design quality through lint, CDC analysis, verification planning, debugging, and design review activities.
Collaborate with cross-functional teams including architecture, RTL design, verification, physical design, and firmware.
Experience developing microarchitecture and RTL for processors, SoCs, or complex IP blocks (preferred).
Experience developing embedded software or firmware in C/C++ (preferred).
Knowledge of digital design fundamentals, low-power design strategies, and processor power management architectures (preferred).
Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (preferred).

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