Principal CPU Physical Design Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $216,600–$325,000 / yr
Posted: 35 days ago
Freshness: Confirmed live today
Closes: Mar 21, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k

This role $271k

$143k $345k

below market most similar roles pay here above market

This role pays more than 94% of similar roles. Most pay $177,250–$231,187 — the blue band above. At the midpoint, this role pays about $271k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Principal CPU Physical Design Engineer

Role Posting Log in to save

The Principal CPU Physical Design Engineer joins the CPU Engineering team to drive the implementation of next-generation CPU cores at advanced nodes. This role involves owning critical portions of CPU implementation from RTL to GDS, with a primary focus on PPA convergence and design quality. The engineer will perform timing, power, and area optimizations for high-frequency subsystems while solving complex silicon problems like congestion, variability, EM/IR, and power integrity. Key responsibilities include developing methodologies, flows, and automation to improve scalability and collaborating with EDA vendors. Required skills include full RTL-to-GDSII implementation experience, including synthesis, place and route, STA, and signoff. Candidates should possess scripting proficiency in TCL or Python and experience with Synopsys or Cadence tools to address CPU-specific design challenges.

Skills

ASIC SoC Physical Design RTL-to-GDSII Synthesis Place & Route STA Signoff Timing Closure Power Optimization TCL Python Synopsys Cadence PPA EM/IR Power Integrity

What you'll do

Own critical portions of CPU implementation from RTL to GDS with a focus on PPA convergence.
Drive timing, power, and area optimization for high-frequency, complex CPU subsystems.
Solve hard silicon problems including timing closure, congestion, variability, EM/IR, and power integrity.
Develop and deploy methodologies, flows, and automation to improve scalability and Quality of Results.
Influence EDA vendors and CAD teams to push tool capabilities for advanced nodes.
Contribute to next-generation design strategies for advanced semiconductor nodes.
Mentor junior engineers and help raise the technical bar of the engineering team.

What we're looking for

10+ years of experience in ASIC/SoC Physical Design.
Bachelor's degree in a related field and 8+ years of engineering experience, OR Master's degree and 7+ years, OR PhD and 6+ years.
Strong experience with full RTL-to-GDSII implementation including synthesis, place & route, STA, and signoff.
Experience in timing closure and power optimization.
Scripting skills in TCL, Python, or similar.
Experience working on CPU cores or other high-performance designs (preferred).
Expertise in advanced nodes such as 7nm, 5nm, 3nm or below (preferred).
Hands-on experience with industry-standard tools like Synopsys or Cadence (preferred).

Similar roles

CPU Physical Design Engineer

Qualcomm

San Diego, CA 34 days ago $129,500–$194,300

CPU) design Verilog RTL Synthesis Place and Route GDS Logic Design Power Analysis Tapeout Microarchitecture Physical Design

2+ yrs exp

Save

CPU Physical Design Engineer

Qualcomm

Austin, TX 40 days ago $216,600–$325,000

CPU Design micro-architecture Logic Design Physical Design Verilog VHDL C C++ Python Perl Formal Verification Silicon Validation Synthesis Design Verification Computer Architecture Waveform Debugging

8+ yrs exp

Save

CPU Physical Design CAD Engineer (Senior Staff)

Qualcomm

Santa Clara, CA +2 21 days ago $209,300–$313,900

Tcl Python Cadence Innovus Place-and-Route Physical Design Timing Analysis Physical Verification Digital Design Automation PPA 5nm Hardware Engineering

6+ yrs exp

Save

CPU Physical Design Engineer

Qualcomm

Austin, TX 40 days ago $129,500–$194,300

CPU Design micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Formal Verification Silicon Validation Emulation Computer Architecture Physical Design

2+ yrs exp

Save

Senior SOC/ASIC Physical Design Engineer

SpaceX

Austin, TX +2 154 days ago

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route Physical Verification Electromigration Voltage Drop Logic Equivalency FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools

5+ yrs exp

Save

Physical Design Engineer

Qualcomm

San Diego, CA 8 days ago $174,400–$261,600

ASIC SoC Physical Design Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python Perl TCL C/C++ Shell Scripting Linux Unix Static Timing Analysis Clock Tree Synthesis DFT Formal Verification RC Extraction IR-drop Analysis

10+ yrs exp

Save