Principal CPU Physical Design Engineer (San Diego, CA)

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$211,900–$317,900 / yr
Posted
5 days ago
Closes
Dec 7, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k
This role $265k
$139k most similar roles pay here $337k

This role pays more than 92% of similar roles. Most pay $168,500–$225,800 — the shaded band above. At the midpoint, this role pays about $265k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 749 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.

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At a glance

TL;DR · Principal CPU Physical Design Engineer (San Diego, CA)

As a CPU Physical Design expert at Qualcomm Technologies, Inc., you will join the cutting-edge semiconductor design team to drive performance and power efficiency in next-generation CPU cores. Your daily responsibilities include owning critical portions of CPU implementation from RTL to GDSII, focusing on PPA convergence and quality, while collaborating with Architecture, RTL, and Circuit teams for co-optimization. You will also develop methodologies and automation tools to enhance design scalability and QoR across projects, influence EDA vendors, and mentor junior engineers. Required skills include 10+ years of ASIC/SoC Physical Design experience, expertise in full RTL-to-GDSII implementation, timing closure, power optimization, and scripting with TCL or Python. Preferred qualifications involve hands-on experience with Synopsys/Cadence tools, advanced node design (7nm, 5nm, 3nm), and a deep understanding of PPA trade-offs specific to CPU designs.

What you'll do

  • Own critical portions of CPU implementation from RTL to GDS.
  • Drive timing, power, and area optimization for high-frequency subsystems.
  • Solve hard silicon problems like timing closure and congestion issues.
  • Develop methodologies and automation to improve design quality and scalability.
  • Influence EDA vendors and CAD teams to enhance tool capabilities.
  • Mentor junior engineers and elevate the technical standards of the team.

What we're looking for

  • 10+ years of experience in ASIC/SoC Physical Design
  • Expertise in full RTL-to-GDSII implementation including synthesis, place & route, STA, and signoff
  • Strong experience with timing closure and power optimization
  • Proficiency in scripting languages such as TCL or Python
  • Experience working on CPU cores or other high-performance designs
  • Hands-on experience with industry-standard EDA tools (Synopsys/Cadence)

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