Principal CPU Physical Design Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$211,900–$317,900 / yr
Posted
93 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 7, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $265k
$143k most similar roles pay here $337k

This role pays more than 93% of similar roles. Most pay $177,250–$227,500 — the shaded band above. At the midpoint, this role pays about $265k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Principal CPU Physical Design Engineer

As a Principal CPU Physical Design Engineer within the CPU Engineering group, you will drive the implementation of high-performance CPU cores at advanced nodes. You will own critical portions of the design from RTL to GDS, focusing on PPA convergence and solving complex challenges such as timing closure, congestion, variability, EM/IR, and power integrity. The role involves collaborating with Architecture, RTL, and Circuit teams to optimize designs for high-frequency subsystems while developing automated methodologies and flows to improve scalability. You will utilize industry-standard tools from Synopsys or Cadence and apply scripting skills in TCL or Python. This position addresses the technical challenges of advanced semiconductor nodes, specifically focusing on performance, power efficiency, and scalability for next-generation CPU architectures. Your work directly influences architecture trade-offs and implementation strategies to ensure successful silicon results.

What you'll do

  • Own critical portions of CPU implementation from RTL to GDS with a focus on PPA convergence.
  • Drive timing, power, and area optimization for high-frequency, complex CPU subsystems.
  • Resolve technical challenges including timing closure, congestion, variability, EM/IR, and power integrity.
  • Develop and deploy methodologies, flows, and automation to improve scalability and quality of results.
  • Influence EDA vendors and CAD teams to enhance tool capabilities and design strategies.
  • Collaborate with Architecture, RTL, and Circuit teams to co-optimize designs for physical implementation.
  • Mentor junior engineers and elevate the technical standards of the engineering team.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 8+ years of experience in Hardware, Software, Electrical, or Systems Engineering with a Bachelor's degree.
  • 7+ years of experience in Hardware, Software, Electrical, or Systems Engineering with a Master's degree.
  • 6+ years of experience in Hardware, Software, Electrical, or Systems Engineering with a PhD.
  • 10+ years of experience in ASIC/SoC Physical Design.
  • Proficiency in RTL-to-GDSII implementation including synthesis, place and route, STA, and signoff.
  • Experience in timing closure, power optimization, and scripting using TCL or Python.

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