Senior DTCO Engineer, CPU Physical Design

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXHillsboro, ORDurham, NC
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
8 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $198k
This role $177k
$123k $258k
below market most similar roles pay here above market

This role pays less than 64% of similar roles. Most pay $172,000–$223,000 — the blue band above. At the midpoint, this role pays about $177k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1626 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1115 roles with salary data.

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At a glance

TL;DR · Senior DTCO Engineer, CPU Physical Design

Role Posting Log in to save

The Senior DTCO Engineer, CPU Physical Design joins a dynamic team to evaluate advanced semiconductor foundry nodes and optimize next-generation CPU microarchitecture. The role involves coordinating between foundry partners, IP development, and hardware design teams during early development phases to explore target technology nodes. Key responsibilities include running synthesis, place-and-route, and static timing analysis to assess how process features affect power, performance, and area. The engineer will use early pathfinding blocks to identify implementation bottlenecks and project technology-node scaling while evaluating competitive products and benchmarks to understand design trade-offs. Required skills include a background in advanced-node silicon design and physical-design methodology, proficiency in Python, Tcl, Perl, or similar scripting languages, and experience with AI tools to solve complex technical trade-offs in high-performance computing.

Skills

CPU Physical Design DTCO Synthesis Place-and-Route Static Timing Analysis PPA Python Tcl Perl timing-closure Silicon Design AI Tools Hardware Design Pathfinding

What you'll do

  • Evaluate advanced semiconductor foundry nodes to optimize next-generation CPU microarchitecture.
  • Run synthesis, place-and-route, and static timing analysis to assess power, performance, and area.
  • Coordinate with foundry partners, IP development, and hardware design teams during early development phases.
  • Use early pathfinding blocks to identify implementation bottlenecks and project technology-node scaling.
  • Evaluate competitive products and benchmarks to understand technology and design trade-offs.
  • Analyze physical implementation constraints to develop technology solutions that improve PPA.
  • Translate test-chip or silicon data into measurable product improvements.

What we're looking for

  • Master’s or Ph.D. in Electrical Engineering, or a related field, or equivalent experience.
  • 5+ years of relevant experience.
  • Strong background in advanced-node silicon design and physical-design methodology.
  • Ability to analyze physical implementation constraints and develop technology solutions to improve PPA.
  • Proficiency with Python, Tcl, Perl, or similar scripting languages, as well as AI tools.
  • Experience with DTCO or technology pathfinding for high-performance CPUs, GPUs, or AI accelerators (preferred).
  • Expertise in advanced circuit and physical-design optimization, clocking, memory, or timing-closure techniques (preferred).
  • Track record of translating test-chip or silicon data into measurable product improvements (preferred).

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