CPU Design Methodology Engineer

Nvidia

Confirmed live 2 days ago High trust

Remote

Quick summary

Work type: Remote
Location: Hillsboro, ORAustin, TXSanta Clara, CA
Salary: $168,000–$264,500 / yr
Posted: 24 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $195k

This role $216k

$137k most similar roles pay here $278k

This role pays more than 71% of similar roles. Most pay $162,000–$227,350 — the shaded band above. At the midpoint, this role pays about $216k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · CPU Design Methodology Engineer

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The Senior CPU Design Methodology Engineer joins the NVIDIA CPU team to focus on SOC design automation, RTL integration, and chip build and assembly. In this role, you will define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner while identifying inefficiencies in the front-end chip implementation process. You will own front-end design quality checks and reviews to ensure high-quality RTL for physical design teams. The position requires expertise in Verilog, SystemVerilog, UVM, and SoC integration flows, alongside strong coding skills in Perl or Python. Candidates must possess experience in synthesis and physical design as a plus. This role addresses the technical challenge of managing complex chip designs with billions of transistors to meet growing computing demands through optimized automation solutions and cross-functional collaboration with various engineering teams.

Skills

SoC Design RTL Verilog System Verilog UVM Python Perl Synthesis Physical Design Design Automation DFT CAD Scripting

What you'll do

Develop system-level methodologies and tools to build SoCs in an efficient and scalable manner.
Identify inefficiencies in the front-end chip implementation process and propose technical improvements.
Own front-end design quality checks and reviews to ensure high-quality RTL for physical design teams.
Create automation solutions to optimize the SoC creation process.
Integrate complex chips by coordinating with ASIC, Physical Design, CAD, and DFT teams.
Develop scripts using Perl or Python to automate chip design workflows.

What we're looking for

Master's degree in Computer Engineering, Electrical Engineering, or equivalent experience.
8+ years of experience in chip design specializing in SoC integration and design automation.
Experience in RTL design using Verilog and verification using UVM and SystemVerilog.
Proficiency in System-on-Chip design/integration flow and design automation.
Strong coding skills in Perl, Python, or other industry-standard scripting languages.
Excellent analytical and problem-solving skills.
Good interpersonal skills.
Experience in synthesis and physical design (preferred).