CPU Design Methodology Engineer

Nvidia

Confirmed live today High trust

Remote

Quick summary

Work type: Remote
Location: Hillsboro, ORAustin, TXAZSanta Clara, CA
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 36 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $204k

This role $216k

$137k $278k

below market most similar roles pay here above market

This role pays more than 62% of similar roles. Most pay $164,313–$244,250 — the blue band above. At the midpoint, this role pays about $216k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · CPU Design Methodology Engineer

Role Posting Log in to save

The Senior CPU Design Methodology Engineer joins the CPU team to focus on SOC design automation, RTL integration, and chip build and assembly. In this role, you will define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner. You will identify inefficiencies in the front-end chip implementation process, propose improvements, and own front-end design quality checks to provide high-quality RTL to the physical design team. The position requires expertise in RTL design using Verilog, verification with UVM and SystemVerilog, and SOC integration flows. You must possess strong coding skills in Perl and Python. This role addresses the technical challenge of packing tens of billions of transistors into a footprint that meets growing computing demands while optimizing the SOC creation process.

Skills

SOC Design RTL Design Verilog System Verilog UVM Design Automation Python Perl Synthesis Physical Design DFT Chip Build and Assembly Front-end Design Quality Checks

What you'll do

Define and develop system-level methodologies and tools to build SOCs efficiently and scalably.
Identify inefficiencies in the front-end chip implementation process and propose technical improvements.
Own front-end design quality checks and reviews to ensure high-quality RTL for physical design.
Develop automation solutions to optimize the SOC creation process.
Manage RTL integration and chip build and assembly processes.
Interact with unit-level ASIC, Physical Design, CAD, Package Design, Software, and DFT teams.

What we're looking for

Master's degree in Computer or Electrical Engineering or equivalent experience.
8+ years of experience in chip design, specializing in SOC integration and design automation.
Experience in RTL design using Verilog.
Experience in verification using UVM and SystemVerilog.
Experience in System-On-Chip design/integration flow and design automation.
Strong coding skills in Perl, Python, or other industry-standard scripting languages.
Excellent analytical and problem-solving skills.
Experience in synthesis and physical design (preferred).

Save