Director, CPU RTL Design Engineering

Amd

Confirmed live today High trust
Remote

Quick summary

Work type
Remote
Location
Santa Clara, CA
Salary
$248,800–$373,200 / yr
Posted
8 days ago
Freshness
Confirmed live today
Closes
Aug 14, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $213k
This role $311k
$140k most similar roles pay here $398k

This role pays more than 96% of similar roles. Most pay $177,250–$248,781 — the shaded band above. At the midpoint, this role pays about $311k versus about $213k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 512 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 512 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Director, CPU RTL Design Engineering

As Director, CPU RTL Design Engineering, you will serve as a technical leader managing a high-performing team of engineers to design state-of-the-art x86 microprocessors. You will coordinate teams across multiple design blocks, drive project goals and dependencies with architecture, verification, and physical design teams, and develop implementation strategies for quality, timely solutions. The role involves resolving complex design problems, participating in technical reviews of specifications, and overseeing the silicon development lifecycle through tapeout. Key requirements include expertise in computer architecture, processor pipelines, memory hierarchy, and Instruction Set Architecture design. You will utilize RTL and logic design methodologies while leveraging scripting and automation languages such as Ruby, Python, or Perl. This role focuses on developing next-generation CPU designs for the global x86 market, spanning server, desktop, and laptop products.

What you'll do

  • Lead and coordinate a team of RTL design engineers across multiple design blocks.
  • Drive project design goals and dependencies with architecture, verification, and physical design teams.
  • Develop implementation strategies to deliver quality, timely, and cost-effective microprocessor solutions.
  • Provide technical leadership to resolve complex design problems in a dynamic environment.
  • Participate in technical reviews of specifications, designs, and test plans to ensure quality objectives.
  • Manage the execution of multiple complex silicon designs through the tapeout process.
  • Drive critical design decisions for next-generation x86 CPU architectures.

What we're looking for

  • BS or MS in EE, CE, or CS and relevant experience.
  • Proven experience leading and developing high performing silicon design engineering teams (preferred).
  • Demonstrated success leading multiple complex silicon designs through tapeout, ideally in a CPU or advanced processor environment (preferred).
  • Strong technical leadership to resolve complex design problems and drive decisions across architecture, verification, and physical design teams (preferred).
  • Expertise in computer architecture, processor pipeline, and memory hierarchy (preferred).
  • Experience designing Instruction Set Architecture of a complex microprocessor (preferred).
  • Extensive experience with RTL and logic design, design methodology, and the silicon development lifecycle (preferred).
  • Proficiency with scripting and automation languages such as Ruby, Python, or Perl (preferred).

More like this

Similar roles

CPU Core RTL Design Engineer

Amd

Austin, TX 87 days ago $178,400–$267,600
Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Timing Closure Python Tcl DFT Power Management Post-silicon Debug Place-and-Route
Hybrid

CPU-Core RTL Director

Qualcomm

Austin, TX +1 16 days ago $228,400–$342,600
RTL SystemVerilog Microarchitecture CPU Design Silicon Debug Timing Closure Power Optimization DFT CAD Emulation Physical Design SIMD Memory Hierarchy Low-power Design AI-assisted design workflows
8+ yrs exp

Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 6 days ago $101,400–$152,200
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout