CPU Physical Design Timing Engineer
Qualcomm
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How this pay compares to similar roles
This role pays more than 65% of similar roles. Most pay $177,250–$242,187 — the blue band above. At the midpoint, this role pays about $220k versus about $210k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 575 open roles on FindRole.
Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.
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At a glance
As a CPU Server Physical Design Timing Engineer within the CPU Engineering group, you will define, develop, and drive CPU timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to develop timing constraints and drive implementation to meet aggressive power, area, and performance goals. Your daily responsibilities include STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs. You will perform timing analysis, validation, and debug across multiple PVT conditions, while coding automation scripts to enable CPU timing infrastructure. You must utilize industry-standard tools including PT, Tempus, ICC2, and Innovus. Required skills include proficiency in TCL, Perl, and Python, along with expertise in AOCV/POCV concepts, signal integrity, and layout parasitic extraction on N2/N3 technology nodes.
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