CPU Physical Design Timing Engineer
Qualcomm
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How this pay compares to similar roles
This role pays more than 63% of similar roles. Most pay $169,625–$225,800 — the shaded band above. At the midpoint, this role pays about $209k versus about $198k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 623 open roles on FindRole.
Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.
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At a glance
As a CPU Server Physical Design Timing Engineer on the CPU Engineering team, you will define, develop, and drive timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to establish timing constraints and implement designs that meet aggressive power, area, and performance goals. Your daily responsibilities include performing STA setup, convergence, and signoff for multi-mode, multi-voltage domain designs while conducting analysis across various PVT conditions. You will also develop automation scripts to enhance timing infrastructure and methodology. The role requires proficiency in industry tools such as PrimeTime, Tempus, ICC2, and Innovus, along with expert scripting skills in TCL, Perl, and Python. This position focuses on solving complex timing miscorrelations and optimizing PPA goals for high-performance CPU designs across advanced N2/N3 technology nodes.
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