CPU Server Physical Design Timing Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$175,600–$263,400 / yr
Posted
35 days ago
Freshness
Confirmed live today
Closes
Mar 21, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $210k
This role $220k
$137k $278k
below market most similar roles pay here above market

This role pays more than 65% of similar roles. Most pay $177,250–$242,187 — the blue band above. At the midpoint, this role pays about $220k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · CPU Server Physical Design Timing Engineer

As a CPU Server Physical Design Timing Engineer within the CPU Engineering group, you will define, develop, and drive CPU timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to develop timing constraints and drive implementation to meet aggressive power, area, and performance goals. Your daily responsibilities include STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs. You will perform timing analysis, validation, and debug across multiple PVT conditions, while coding automation scripts to enable CPU timing infrastructure. You must utilize industry-standard tools including PT, Tempus, ICC2, and Innovus. Required skills include proficiency in TCL, Perl, and Python, along with expertise in AOCV/POCV concepts, signal integrity, and layout parasitic extraction on N2/N3 technology nodes.

What you'll do

  • Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage Oryon CPU Core designs.
  • Conduct timing analysis, validation, and debug across multiple PVT conditions using PT and Tempus tools.
  • Execute Primetime and Tempus for STA flow optimization and perform Spice to STA correlation.
  • Identify root causes of timing miscorrelation at different design levels and propose technical solutions.
  • Evaluate various timing methodologies and tools across different designs and technology nodes.
  • Develop automation scripts using TCL, Perl, or Python for STA and physical design tools.
  • Define and drive timing constraints to meet aggressive power, area, and performance goals.

What we're looking for

  • Bachelor's degree in a related field and 4+ years of relevant engineering experience.
  • Master's degree in a related field and 3+ years of relevant engineering experience.
  • PhD in a related field and 2+ years of relevant engineering experience.
  • Familiarity with digital flow design implementation from RTL to GDS using ICC, Innovus, and PT/Tempus.
  • Strong experience in design automation using TCL, Perl, and Python.
  • Good technical writing and communication skills for cross-collaborative environments.
  • Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, and managing timing constraints (preferred).
  • Hands-on experience with Prime-time and Tempus tools, and knowledge of ASIC back-end design flows (preferred).

More like this

Similar roles

CPU Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 34 days ago $209,300–$313,900
STA TCL Python Perl PrimeTime Tempus ICC2 Innovus RTL GDS Spice ASIC CTS AOCV POCV Signal Integrity Layout Parasitic Extraction
6+ yrs exp

CPU Physical Design Timing Engineer

Qualcomm

Austin, TX 40 days ago $129,500–$194,300
STA TCL Perl Python PrimeTime Tempus ICC2 Innovus RTL GDS Spice Signal Integrity Layout Parasitic Extraction CTS AOCV POCV
2+ yrs exp

CPU Server Physical Design Clock Engineer

Qualcomm

Santa Clara, CA 35 days ago $147,900–$221,900
Physical Design SPICE RTL Circuit Design PLL Jitter Analysis Standard Cell Optimization RC Delay Device Physics Hardware Engineering Electrical Engineering
2+ yrs exp

CPU Server Physical Design Clock Engineer

Qualcomm

Austin, TX +1 40 days ago $155,400–$233,200
Physical Design SPICE RTL Circuit Design Standard Cell Optimization PLL Jitter Analysis RC Delay Device Physics Chip Physical Design Deep Submicron Process
4+ yrs exp

CPU Design Timing Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Static Timing Analysis PrimeTime Tempus TCL Python Perl SDC RTL Logic Synthesis PnR Parasitic Extraction Logic Equivalence clock-domain crossing Assertion Based Verification CPU Microarchitecture
10+ yrs exp

CPU Design Timing Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Static Timing Analysis PrimeTime Tempus TCL Python Perl SDC RTL Logic Synthesis PnR Parasitic Extraction Logic Equivalence clock-domain crossing Assertion Based Verification CPU Microarchitecture
10+ yrs exp