CPU Server Physical Design Timing Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$167,100–$250,700 / yr
Posted
35 days ago
Freshness
Confirmed live yesterday
Closes
Feb 3, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $198k
This role $209k
$136k most similar roles pay here $263k

This role pays more than 63% of similar roles. Most pay $169,625–$225,800 — the shaded band above. At the midpoint, this role pays about $209k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU Server Physical Design Timing Engineer

As a CPU Server Physical Design Timing Engineer on the CPU Engineering team, you will define, develop, and drive timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to establish timing constraints and implement designs that meet aggressive power, area, and performance goals. Your daily responsibilities include performing STA setup, convergence, and signoff for multi-mode, multi-voltage domain designs while conducting analysis across various PVT conditions. You will also develop automation scripts to enhance timing infrastructure and methodology. The role requires proficiency in industry tools such as PrimeTime, Tempus, ICC2, and Innovus, along with expert scripting skills in TCL, Perl, and Python. This position focuses on solving complex timing miscorrelations and optimizing PPA goals for high-performance CPU designs across advanced N2/N3 technology nodes.

What you'll do

  • Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
  • Conduct timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus tools.
  • Execute Primetime or Tempus runs to optimize STA flows and perform Spice to STA correlation.
  • Identify root causes of timing miscorrelations at various design levels and propose technical solutions.
  • Evaluate different timing methodologies and tools across various designs and advanced technology nodes.
  • Develop automation scripts using TCL, Perl, or Python to enhance STA and physical design tool workflows.
  • Drive PPA goals for CPU projects by collaborating with microarchitecture, RTL, and implementation teams.

What we're looking for

  • Bachelor's degree plus 4 years of experience, Master's plus 3 years, or PhD plus 2 years in a relevant engineering field.
  • Experience with STA setup, convergence, and signoff for multi-mode, multi-voltage domain designs.
  • Proficiency in timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus.
  • Ability to perform Spice to STA correlation and identify root causes of timing miscorrelation.
  • Strong experience in design automation using TCL, Perl, or Python.
  • Familiarity with digital flow design implementation from RTL to GDS using ICC and Innovus.
  • Expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, and managing timing constraints (preferred).
  • Knowledge of cross-talk noise, Signal Integrity, Layout Parasitic Extraction, and device physics (preferred).

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