below marketmost similar roles pay hereabove market
This role pays less than
79%
of similar roles. Most pay
$169,625–$227,500
— the blue band above.
At the midpoint, this role pays about
$162k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
The CPU Top-Level Design Verification Engineer joins a hardware team to own the verification methodology, tools, and flow for a high-performance, lower-power processor design. The engineer will work closely with RTL designers and verification engineers to define methodologies, develop test plans, and build test benches and environments. Daily responsibilities include developing tests in assembly and C/C++, maintaining efficient testbench environments, and creating coverage monitors to analyze and ensure test case completion. Key technical requirements include proficiency in SystemVerilog, C, C++, and Python for automation and EDA tool integration. The role requires a strong understanding of computer architecture, including instruction set architectures, pipeline design, and cache hierarchies, to solve complex hardware design and verification challenges while driving coverage convergence for sign-off.
Define verification methodologies for low power complex processor designs.
Develop comprehensive test plans, test benches, and verification environments.
Write hardware tests using assembly, C, and C++.
Develop and maintain tools and flows for advanced verification methodologies.
Create and maintain efficient testbench environments.
Develop coverage monitors and analyze metrics to ensure plan completion.
Run large-scale random regression suites and perform systematic failure analysis.
Develop coverage models to achieve verification closure and sign-off criteria.
What we're looking for
Minimum BS degree.
BS in Electrical Engineering, Computer Science, or Computer Engineering (preferred).
Strong understanding of processor design, instruction set architectures, pipeline design, cache hierarchies, and memory systems (preferred).
Experience creating efficient, synthesizable RTL code with understanding of timing closure, area optimization, and power-aware design techniques (preferred).
Proficiency in SystemVerilog including advanced features like interfaces, assertions, and verification constructs (preferred).
Strong software development capabilities in C, C++, and Python for automation and tool development (preferred).
Experience with build systems, regression frameworks, and maintaining verification infrastructure (preferred).
Experience running large-scale random regression suites and performing failure analysis and waveform analysis (preferred).