CPU Core RTL Design Engineer

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $144,800–$217,200 / yr
Posted: 5 days ago
Freshness: Confirmed live today
Closes: Oct 21, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $204k

This role $181k

$131k $278k

below market most similar roles pay here above market

This role pays less than 65% of similar roles. Most pay $168,500–$239,462 — the blue band above. At the midpoint, this role pays about $181k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · CPU Core RTL Design Engineer

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The CPU Core RTL Design Engineer joins the central core RTL team to design and optimize next-generation high-performance processor cores for client, server, and AI platforms. The role involves designing and implementing RTL for CPU core pipeline components, contributing to microarchitecture definitions, and analyzing performance, power, and timing characteristics. Key responsibilities include supporting design verification, synthesis, timing closure, and physical design while debugging pre-silicon and post-silicon issues. Candidates should possess experience with Verilog and SystemVerilog RTL development in CPU, SoC, or ASIC environments. Required skills include knowledge of out-of-order cores, load/store, cache hierarchy, and branch prediction. Proficiency in scripting with Python or Tcl, along with understanding of DFT, clocking, and power management, is essential for solving complex technical challenges in modern processor design.

Skills

Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Cache Hierarchy TLB Branch Prediction

What you'll do

Design and implement RTL for CPU core pipeline components and related logic.
Contribute to the microarchitecture definition for next-generation processor cores.
Analyze and improve performance, power, and timing characteristics of designs.
Support design verification, synthesis, timing closure, and physical design efforts.
Debug and resolve pre-silicon and post-silicon issues.
Contribute to scalable RTL methodologies, libraries, and best practices.

What we're looking for

Design and implement RTL for CPU core pipeline components and related logic.
Contribute to microarchitecture definition for next-generation processor cores.
Analyze and improve performance, power, and timing characteristics.
Debug and resolve pre-silicon and post-silicon issues.
Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments (preferred).
Strong understanding of modern CPU architecture, especially out-of-order cores (preferred).
Expertise in logic design and high-speed processor pipeline development (preferred).
Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field (preferred).

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