CPU Physical Design Timing Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$198,700–$298,100 / yr
Posted
9 days ago
Freshness
Confirmed live yesterday
Closes
Mar 1, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $248k
$133k most similar roles pay here $316k

This role pays more than 85% of similar roles. Most pay $174,900–$216,250 — the shaded band above. At the midpoint, this role pays about $248k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU Physical Design Timing Engineer

As a CPU Physical Design Timing Engineer, you will join the CPU Engineering team to define, develop, and drive timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to establish timing constraints and implement designs that meet aggressive power, area, and performance goals. Your daily responsibilities include performing STA setup, convergence, and signoff for multi-mode, multi-voltage domain designs while conducting timing analysis across various PVT conditions. You will also develop automation scripts using TCL, Perl, or Python to enhance CPU timing infrastructure and methodology. The role requires proficiency with industry tools such as PrimeTime, Tempus, ICC, and Innovus. You will solve complex technical challenges involving signal integrity, layout parasitic extraction, and Spice-to-STA correlation while working on advanced technology nodes like N2 and N3 to ensure high-performance CPU execution.

What you'll do

  • Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
  • Conduct timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus tools.
  • Execute Primetime or Tempus for STA flow optimization and perform Spice to STA correlation.
  • Identify root causes of timing miscorrelation at various design levels and propose technical solutions.
  • Evaluate various timing methodologies and tools across different designs and advanced technology nodes.
  • Develop automation scripts using TCL, Perl, or Python to support CPU STA signoff flows and infrastructure.
  • Define and manage timing constraints to meet aggressive power, area, and performance goals.

What we're looking for

  • Bachelor's degree with 6+ years of experience, Master's with 5+ years, or PhD with 4+ years in a relevant engineering field.
  • Experience in STA setup, convergence, and signoff for multi-mode, multi-voltage domain designs.
  • Proficiency in timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus tools.
  • Expertise in STA basics including AOCV/POCV concepts, CTS, and managing timing constraints.
  • Experience with ASIC back-end design flows and tools such as ICC2 or Innovus.
  • Advanced automation skills using TCL, Perl, and Python to develop scripts for STA signoff flow and methodology.
  • Knowledge of crosstalk noise, Signal Integrity, Layout Parasitic Extraction, and device physics.
  • Strong technical writing and communication skills for a cross-collaborative environment.

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