CPU Physical Design Timing Engineer

What you'll do

• Define and develop timing constraints for Oryon CPU Cores to meet power, area, and performance goals.
• Perform STA setup, convergence, reviews, and signoff for multi-mode and multi-voltage domain designs.
• Conduct timing analysis, validation, and debug across multiple PVT conditions using PT and Tempus tools.
• Execute Primetime and Tempus for STA flow optimization and perform Spice to STA correlation.
• Identify and resolve root causes of timing miscorrelation at various design levels in functional and test modes.
• Develop automation scripts using TCL, Perl, or Python to enable CPU timing infrastructure and signoff flows.
• Evaluate various timing methodologies and tools across different designs and technology nodes.

What we're looking for

• Bachelor's degree and 6+ years of relevant engineering experience, Master's degree and 5+ years, or PhD and 4+ years of experience.
• Excellent automation skills using TCL, Perl, and Python.
• Ability to develop automation scripts for CPU STA signoff flow and methodology.
• Familiarity with digital flow design implementation from RTL to GDS using ICC, Innovus, and PT/Tempus.
• Good technical writing and communication skills for cross-collaborative environments.
• History of framework, tool, or utility development (preferred).
• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, and managing timing constraints (preferred).
• Hands-on experience with Prime-time, Tempus, and driving timing convergence at Chip-level and Hard-Macro level (preferred).