CPU Physical Design CAD Engineer (Senior Staff)

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXSan Diego, CA
Salary
$209,300–$313,900 / yr
Posted
21 days ago
Freshness
Confirmed live yesterday
Closes
Apr 4, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k
This role $262k
$131k $334k
below market most similar roles pay here above market

This role pays more than 97% of similar roles. Most pay $168,200–$227,350 — the blue band above. At the midpoint, this role pays about $262k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · CPU Physical Design CAD Engineer (Senior Staff)

The CPU Physical Design CAD Engineer (Sr Staff) joins the CPU Engineering team to build and support world-class implementation tools and flows. This role focuses on developing, integrating, and releasing new features within a high-performance place-and-route CAD flow to ensure custom CPUs achieve industry-leading power, performance, and area. Key responsibilities include architecting methodology improvements, debugging implementation flows, and collaborating with worldwide physical design teams and EDA vendors. The position requires proficiency in Tcl and Python, experience with automation, and expertise in physical design tasks such as timing sign-off and physical verification. Candidates must have experience with advanced technology nodes at 5nm or lower and be skilled in using industry-standard tools like Cadence Innovus to solve complex silicon design challenges.

What you'll do

  • Develop, integrate, and release new features in the high-performance place-and-route CAD flow.
  • Architect and recommend methodology improvements to optimize silicon power, performance, and area.
  • Maintain, support, and debug implementation flows while resolving project-specific issues.
  • Provide methodology guidance and tools support to worldwide CPU physical design teams.
  • Collaborate with EDA vendors to define roadmaps and resolve tool-specific issues.
  • Manage and regress place-and-route flows for high-performance chips.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of relevant engineering experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of relevant engineering experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant engineering experience.
  • Ten+ years of hands-on experience in place-and-route of high-performance chips in a design or CAD role (preferred).
  • High level of proficiency in Tcl and Python (preferred).
  • Experience with automation (preferred).
  • Experience with a wide variety of Physical Design tasks including place-and-route, analysis, timing sign-off, and PDV (preferred).
  • Experience with advanced technology nodes of 5nm or lower (preferred).

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