CPU Micro-architect/RTL Designer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Austin, TXSanta Clara, CA
Salary
$211,900–$317,900 / yr
Posted
38 days ago
Freshness
Confirmed live yesterday
Closes
Jan 31, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k
This role $265k
$135k most similar roles pay here $338k

This role pays more than 94% of similar roles. Most pay $172,000–$240,000 — the shaded band above. At the midpoint, this role pays about $265k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU Micro-architect/RTL Designer

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As a CPU Micro-architect/RTL Designer within the CPU Engineering team, you will contribute to the development of high performance, low power devices. You will collaborate with chip architects to conceive micro-architecture, conduct performance exploration, and develop detailed specifications from early architectural stages. Your daily responsibilities include RTL ownership, where you will develop, assess, and refine designs to meet specific power, performance, area, and timing goals. Additionally, you will provide support for functional and performance verification while coordinating with multi-functional teams to validate physical design aspects like reliability and testability. The role requires expertise in microprocessor architecture—including branch prediction, out-of-order execution, and memory subsystems—alongside proficiency in Verilog or VHDL, waveform debugging tools, and scripting languages like Perl or Python. You will apply logic design principles and low power techniques to solve complex hardware challenges.

Skills

RTL Design Microarchitecture Verilog VHDL Python Perl Logic Design Waveform Debugging Simulators Instruction Fetch and Decode Branch Prediction Out-of-Order Execution

What you'll do

  • Conduct performance exploration for high-performance strategies in collaboration with the CPU modeling team.
  • Develop microarchitecture specifications from early architectural exploration through detailed research.
  • Own RTL design by developing and refining code to meet power, performance, area, and timing goals.
  • Support the design verification team in executing functional verification strategies.
  • Verify that the RTL design meets established performance targets.
  • Coordinate with multi-functional teams to implement and validate physical design aspects like timing and reliability.

What we're looking for

  • Bachelor's degree with 8+ years of experience in engineering or a related field.
  • Master's degree with 7+ years of experience in engineering or a related field.
  • PhD with 6+ years of experience in engineering or a related field.
  • Thorough knowledge of microprocessor architecture including fetch, decode, branch prediction, and memory subsystems.
  • Knowledge of Verilog and/or VHDL along with experience using simulators and waveform debugging tools.
  • Knowledge of logic design principles regarding timing and power implications.
  • Understanding of low power microarchitecture techniques and high performance trade-offs.
  • Experience using scripting languages such as Perl or Python.

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