CPU Server Physical Design Clock Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$142,200–$213,400 / yr
Posted
66 days ago
Freshness
Confirmed live yesterday
Closes
Jan 3, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k
This role $178k
$132k most similar roles pay here $240k

This role pays less than 57% of similar roles. Most pay $168,500–$223,700 — the shaded band above. At the midpoint, this role pays about $178k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU Server Physical Design Clock Engineer

As a CPU Server Physical Design Clock Engineer within the CPU Engineering group, you will collaborate with microarchitecture, RTL design, CAD, and block level and top level physical design teams to create best in class clocking solutions for next generation CPUs. You will be responsible for driving overall clock generation and distribution methodology while implementing techniques to optimize skew and power. Your daily work involves performing jitter analysis and measurements, providing feedback on necessary fixes, and validating CPU clocking. The role requires expertise in low skew and low power clock construction, including H-tree, mesh, spines, and CTS implementations. You will utilize SPICE simulation for circuit design and verification while applying knowledge of device physics, RC delay, electrical aspects, standard cell optimizations, PLL specifications, and deep submicron process technology nodes to solve complex hardware challenges.

What you'll do

  • Design and implement low skew and low power clock generation and distribution networks.
  • Construct and analyze clock H-trees, meshes, spines, and Clock Tree Synthesis (CTS) implementations.
  • Perform jitter analysis and measurements to provide feedback for necessary design fixes.
  • Develop and drive the overall clock generation and distribution methodology for CPUs.
  • Collaborate with CAD and block-level designers to implement techniques optimizing skew and power.
  • Validate CPU clocking designs in coordination with microarchitecture, RTL, and physical design teams.
  • Conduct SPICE simulations and analysis for circuit design and verification.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 2+ years of experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 1+ year of experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Experience in construction and analysis of low skew and low power clock generation and distribution.
  • Experience in clock H-tree, mesh, spines, and CTS implementations.
  • Proficiency in SPICE simulation and analysis for circuit design and verification.
  • Understanding of device physics, RC delay, and electrical aspects.
  • Expertise in chip physical design, standard cell optimizations, and deep submicron process technology nodes.

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