CPU Server Physical Design Clock Engineer

Qualcomm

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Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$147,900–$221,900 / yr
Posted
35 days ago
Freshness
Confirmed live today
Closes
Mar 21, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $209k
This role $185k
$134k $278k
below market most similar roles pay here above market

This role pays less than 63% of similar roles. Most pay $177,087–$241,750 — the blue band above. At the midpoint, this role pays about $185k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · CPU Server Physical Design Clock Engineer

The CPU Server Physical Design Clock Engineer joins the CPU Engineering group to develop best in class clocking solutions for next generation CPUs. This role involves collaborating with microarchitecture, RTL design, CAD, and block level teams to implement and validate CPU clocking. Key responsibilities include driving clock generation and distribution methodology, performing jitter analysis and measurements, and optimizing for skew and power. The position requires expertise in low skew and low power clock generation, including H-tree, mesh, spines, and CTS implementations. Candidates must possess a strong understanding of device physics, RC delay, and electrical aspects. Required technical skills include proficiency in SPICE simulation and analysis for circuit design and verification, along with experience in standard cell optimizations and deep submicron process technology nodes.

What you'll do

  • Perform jitter analysis and measurements to provide feedback on required fixes for block and top level designs.
  • Implement and validate CPU clocking solutions in coordination with various design teams.
  • Drive the overall clock generation and distribution methodology for the CPU.
  • Implement clocking techniques with CAD and block level designers to optimize skew and power.
  • Construct and analyze low skew and low power clock generation and distribution systems.
  • Implement clock H-tree, mesh, spines, and Clock Tree Synthesis (CTS) structures.
  • Conduct SPICE simulations and analysis for circuit design and verification.

What we're looking for

  • Experience in all aspects of construction and analysis of low skew and low power clock generation and distribution.
  • Experience in clock H-tree, mesh, spines and CTS implementations.
  • Good understanding of device physics, RC delay and electrical aspects.
  • Proficiency in SPICE simulation and analysis for circuit design and verification.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant work experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of relevant work experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • MS in Electrical Engineering and 4+ years of practical experience (preferred).

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