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Verilog SystemVerilog UVM C# C FPGA ASIC QuestaSim Microsemi Actel VHDL Embedded Systems Firmware Git SVN TFS Logic Analyzers Oscilloscopes JTAG ICE +15 more Show less

ASIC Package Design Substrate Interposer Bump Design PCB Design Python Perl SQL PowerBI Data Analytics Data Visualization Semiconductor Theory Transmission Lines +9 more Show less

ASIC Package Design PCB Design Python Perl SQL PowerBI Data Analytics Data Visualization Semiconductor Theory Transmission Lines Design Verification +7 more Show less

ASIC Package Design Substrate Interposer Bump Design PCB Design Python Perl SQL PowerBI Data Analytics Data Visualization Semiconductor Theory Transmission Lines +9 more Show less

ASIC Package Design Substrate Interposer Bump Design PCB Design Python Perl SQL PowerBI Data Analytics Data Visualization Semiconductor Theory +8 more Show less

SoC VLSI RTL DFT Physical Design Emulation Silicon Bring-up Low-power Design Data Analytics Automation ISO26262 Algorithm Development +7 more Show less

ASIC DFT Scan Insertion ATPG Verilog SystemVerilog Python Bash Perl UPF Gate Level Simulation SDF RTL Physical Design Formal Verification DRC Synthesis Silicon Engineering +13 more Show less

ASIC DFT Scan Insertion ATPG Verilog SystemVerilog Python Bash Perl UPF Gate Level Simulation SDF DRC Formal Verification RTL Physical Design +11 more Show less

SystemVerilog UVM Verilog Python Perl C C++ Linux ASIC Design Formal Verification Jasper Gold Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel P4 +16 more Show less

Physical Design STA DFT EDA Tools TCL Verilog RTL Logic Synthesis Low Power Design SERDES DRC Scan Memory BIST Chip Architecture Packaging Tape-out +11 more Show less

ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design +8 more Show less

ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design +8 more Show less

ASIC UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Test Bench Development Object-Oriented Programming Digital Design +8 more Show less

ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification test bench development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Scripting Functional Coverage +9 more Show less

Physical Design STA DFT EDA Tools TCL Verilog RTL Logic Synthesis SERDES Low Power Design Packaging Tape-out DRC Scan Memory BIST Microarchitecture +11 more Show less

Physical Design STA DFT TCL Verilog RTL Logic Synthesis SERDES Low Power Design EDA Tools Tape-out Packaging Logic Simulation DRC Memory BIST +10 more Show less

GPU ASIC PCBA Failure Analysis Root Cause Analysis Python Shell Scripting Linux Windows Oscilloscopes Logic Analyzers Firmware Hardware Verification High-speed Digital Design HBM GDDR PCIe Schematics Data Analysis +13 more Show less

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis +15 more Show less

ASIC Physical Design RTL2GDSII STA EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis Electromigration +15 more Show less

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST FinFET CMOS Python TCL Perl Bash Makefile EDA Tools +15 more Show less