Senior SOC/ASIC Physical Design Engineer

SpaceX

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$175,000–$280,000 / yr
Posted
108 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $228k
$137k most similar roles pay here $295k

This role pays more than 80% of similar roles. Most pay $174,843–$223,175 — the shaded band above. At the midpoint, this role pays about $228k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Senior SOC/ASIC Physical Design Engineer

Role Posting Log in to save

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation silicon for space and ground infrastructure. This role focuses on the physical implementation of chips, where you will perform partition synthesis, floorplanning, power and ground grid generation, place and route, and various signoff checks including static timing analysis, noise, electromigration, and voltage drop. You will also develop automation scripts and collaborate with the ASIC design team to drive architectural feasibility studies and resolve congestion issues. The role requires expertise in RTL2GDSII flows, standard EDA tools, FinFET and CMOS solid state physics, and DFT/Scan/MBIST impacts. Candidates should possess strong scripting skills in csh, bash, Perl, Python, or TCL while navigating the complexities of deep sub-micron processes to enhance the performance and capabilities of the Starlink network.

Skills

ASIC Physical Design RTL2GDSII STA EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis Electromigration

What you'll do

  • Perform partition synthesis and physical implementation steps including floorplanning, power/ground grid generation, and place and route.
  • Execute signoff checks for timing, noise, physical verification, electromigration, voltage drop, and logic equivalency.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Conduct architectural feasibility studies to establish timing, power, and area design targets with the ASIC team.
  • Resolve complex design, timing, and congestion issues while identifying and driving technical solutions.
  • Debug and fix signoff closure issues in static timing analysis (STA) and physical verification flows.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of experience in ASIC and/or physical design flow development.
  • Experience with ASIC/SOC RTL2GDSII physical design and signoff flows.
  • Proficiency with industry standard EDA tools and understanding of their underlying algorithms.
  • Knowledge of deep sub-micron FinFET, CMOS solid state physics, and digital design principles.
  • Understanding of CMOS power dissipation in deep submicron processes and familiarity with CMOS analog circuit design.
  • Knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows.
  • Proficiency in scripting languages such as csh, bash, Perl, Python, TCL, or Makefile.

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