Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $170,000–$230,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $188k

This role $200k

$152k most similar roles pay here $238k

This role pays more than 59% of similar roles. Most pay $160,000–$216,250 — the shaded band above. At the midpoint, this role pays about $200k versus about $188k for comparable roles.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

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As a Senior SOC/ASIC Physical Design Engineer at Silicon Engineering in Sunnyvale, CA, you will be part of a dynamic team responsible for the physical design and signoff flows of complex ASIC/SOC projects. Your daily tasks will include leveraging industry-standard EDA tools to ensure efficient RTL2GDSII processes while adhering to CMOS digital design principles. You will also work closely with DFT/Scan/LBIST methodologies, ensuring their seamless integration into your designs. Ideal candidates should possess strong experience in physical design and signoff flows, along with a deep understanding of EDA tools and CMOS digital design fundamentals. This role demands expertise in standard cell libraries and the ability to navigate intricate physical design challenges at large-scale semiconductor projects.

Skills

RTL2GDSII EDA tools CMOS digital design principles Standard cells DFT Scan MBIST LBIST Physical design flows

What you'll do

Perform ASIC/SOC physical design and signoff flows from RTL to GDSII.
Utilize industry-standard EDA tools for efficient physical design processes.
Apply CMOS digital design principles in creating standard cell libraries.
Implement DFT/Scan/LBIST techniques to enhance testability of designs.
Optimize physical design layouts for performance, power consumption, and area.

What we're looking for

Strong experience in ASIC/SOC physical design and signoff flows.
Proficiency with industry-standard EDA tools and understanding of their algorithms.
Knowledge of CMOS digital design principles and standard cell libraries.
Understanding of DFT/Scan/MBIST/LBIST and their impact on physical design.
Conform to U.S. Department of State ITAR requirements.

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