Senior SOC/ASIC Physical Design Engineer

SpaceX

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Palo Alto, CAAustin, TXIrvine, CASunnyvale, CA
Salary
$175,000–$280,000 / yr
Posted
154 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $228k
$140k $295k
below market most similar roles pay here above market

This role pays more than 78% of similar roles. Most pay $177,250–$227,500 — the blue band above. At the midpoint, this role pays about $228k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · Senior SOC/ASIC Physical Design Engineer

Role Posting Log in to save

The Sr. SOC/ASIC Physical Design Engineer joins the Silicon Engineering team to develop next-generation silicon for space and ground infrastructures. Working with cross-disciplinary teams, the engineer performs partition synthesis, floorplanning, power/ground grid generation, place and route, and various signoff checks including timing, noise, physical verification, electromigration, and voltage drop. The role involves developing physical design methodologies, automation scripts, and driving architectural feasibility studies to resolve design, timing, and congestion issues. Key technical requirements include experience with ASIC/SOC RTL2GDSII flows, industry-standard EDA tools, deep sub-micron FinFET and CMOS solid state physics, and CMOS digital design principles. Proficiency in scripting languages like Python, Perl, TCL, and Makefile is required to support the development of chips enabling global connectivity for the Starlink network.

Skills

ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop

What you'll do

  • Perform partition synthesis, floorplanning, power/ground grid generation, place and route, and physical verification.
  • Execute signoff checks for timing, noise, electromigration, voltage drop, and logic equivalency.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Conduct architectural feasibility studies to develop timing, power, and area design targets.
  • Explore RTL and design tradeoffs to ensure hardware performance and feasibility.
  • Resolve design, timing, and congestion issues while identifying and driving technical solutions.
  • Debug and fix signoff closure issues in static timing analysis and physical verification flows.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of ASIC and/or physical design flow development experience in industry.
  • Ability to work extended hours and weekends as needed to meet critical project milestones.
  • Applicant must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows (preferred).
  • Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms (preferred).
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics (preferred).
  • Knowledge of CMOS digital design principles, standard cell libraries, and power dissipation (preferred).

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