Senior Custom ASIC Engineering Lead

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Posted
43 days ago
Freshness
Confirmed live yesterday
Closes
Jan 26, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $187k
$133k most similar roles pay here $246k

This role pays less than 55% of similar roles. Most pay $175,000–$227,300 — the shaded band above. At the midpoint, this role pays about $187k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Senior Custom ASIC Engineering Lead

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The Senior Custom ASIC Engineering Lead joins the ASIC Products Division to guide customer teams designing complex chips for AI, HPC, networking, and storage. This role involves managing external customer programs from inception through production, including RFQs, design, test, packaging, and fabrication. You will advise customers on EDA flows and design methodologies while proactively identifying risks to quality and project schedules. Day-to-day responsibilities include executing physical design flows to ensure tape-in netlists meet stringent standards and collaborating with cross-functional teams across marketing and legal departments. Required expertise includes multiple tape-outs in advanced nodes, PPA tradeoff analysis, low power design, and proficiency in STA, logic simulation, and packaging. Technical skills required include experience with EDA tools and programming in TCL, shell, and other scripting languages to solve critical infrastructure chip challenges.

Skills

Physical Design STA DFT EDA Tools TCL Verilog RTL Logic Synthesis Low Power Design SERDES DRC Scan Memory BIST Chip Architecture Packaging Tape-out

What you'll do

  • Manage external customer ASIC programs from inception through fabrication, bring-up, and production.
  • Advise customers on best practices regarding EDA tools, design flows, and methodologies.
  • Proactively identify risks to design quality and project schedules to execute mitigation actions.
  • Execute physical design flows to ensure customer netlists meet strict tape-out quality standards.
  • Analyze PPA tradeoffs across various library components and architectures.
  • Provide technical deep-dives for engineers and high-level summaries for management.
  • Participate in cross-functional discussions with marketing, sales, legal, and regulatory teams.

What we're looking for

  • Bachelor's degree and 12+ years of related experience, or a Master's degree and 10+ years of related experience.
  • Experience with multiple tape-outs in advanced technology nodes.
  • Expertise in physical design, STA, DFT, and packaging.
  • Ability to analyze PPA tradeoffs among various library components and architectures.
  • Knowledge of low power design and power management.
  • Proficiency in EDA tools, design flows for physical design, logic simulation, test, and packaging.
  • Programming skills in TCL, shell, and other scripting languages.
  • Experience with SERDES communications protocols, Verilog RTL coding, and DFT methods like scan and memory BIST.

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