Senior ASIC Design Verification Engineer

SpaceX

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Palo Alto, CA
Salary
$175,000–$280,000 / yr
Posted
105 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $228k
$135k $296k
below market most similar roles pay here above market

This role pays more than 82% of similar roles. Most pay $165,648–$217,500 — the blue band above. At the midpoint, this role pays about $228k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer

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The Sr. ASIC Design Verification Engineer joins the Silicon Engineering team to develop next-generation ASICs for space and ground infrastructures. This role focuses on digital ASIC verification at both the block and system levels to expand the performance and capabilities of the Starlink network. Key responsibilities include writing and reviewing test plans, developing test harnesses and sequences, running regressions, and achieving code and functional coverage closure. The engineer will also contribute to pre-silicon verification, chip bring-up, and post-silicon validation. Required skills include design verification and test bench development experience, with preferred expertise in UVM/OVM/VMM methodologies, object-oriented programming, constrained random verification, and Python for automation. The work involves solving complex technical problems to provide reliable broadband internet connectivity in previously unavailable locations.

Skills

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage

What you'll do

  • Perform digital ASIC verification at both the block and system levels.
  • Write and review comprehensive test plans, test harnesses, and test sequences.
  • Execute test plans and run regressions to achieve code and functional coverage closure.
  • Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
  • Execute all necessary steps to fully verify complex digital designs independently.
  • Develop and implement coverage models to analyze verification results.

What we're looking for

  • Bachelor’s degree in electrical engineering or computer engineering.
  • 5+ years of experience with design verification and test bench development.
  • Ability to work extended hours and weekends as needed to meet critical milestones.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Advanced degree in electrical engineering or computer engineering (preferred).
  • Experience with verification methodologies such as UVM/OVM/VMM (preferred).
  • Strong object-oriented programming, coding, and problem-solving skills (preferred).
  • Experience with constrained random verification, scripting languages like Python, RTL design, and post-silicon validation (preferred).

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