ASIC/SOC DFT Engineer

SpaceX

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Work type
On-site
Location
Austin, TXPalo Alto, CA
Posted
82 days ago
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Confirmed live today
Nearby
99+ roles within 25 mi

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

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TL;DR · ASIC/SOC DFT Engineer

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ASIC/SOC DFT Engineer (Silicon Engineering) works within the Silicon Engineering team to develop next-generation ASICs for space and ground infrastructures. The role involves evaluating design readiness for scan insertion using RTL and physical design Scan Design Rule Check tools, integrating and verifying DFT fabrics and IP within subsystems, and refining scan insertion recipes for maximum coverage. Key responsibilities include running ATPG analysis, debugging non-timing and SDF annotated gate level simulations, and creating ATPG content for post-silicon testing. The engineer must collaborate with circuit physical design, ATPG, and manufacturing teams to ensure high-quality scan coverage. Required skills include experience with ASICs, scan insertion, and DFT setup. Preferred competencies include Verilog/SystemVerilog, UPF, formal verification, DRC rule checking, and scripting in csh/bash, Perl, or Python.

Skills

ASIC DFT ATPG Verilog SystemVerilog Python Perl Bash UPF RTL Gate Level Simulation SDF DRC Formal Verification Synthesis Scan Insertion

What you'll do

  • Evaluate design readiness for scan insertion using RTL and physical design DRC tools.
  • Integrate and verify Design for Test (DFT) fabrics and IP within subsystems.
  • Run scan insertion through synthesis tools and refine recipes to maximize coverage.
  • Perform ATPG analysis to ensure quality scan chain construction and meet coverage goals.
  • Run and debug non-timing and SDF annotated gate level simulations.
  • Create and validate ATPG content for post-silicon testing through gate level simulation.
  • Coordinate with physical design and manufacturing teams to achieve high-quality silicon scan coverage.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 1+ years of professional experience working with ASICs.
  • Experience in scan insertion or DFT setup.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Understanding of ASIC design flow, methodologies, physical design, and verification (preferred).
  • Experience with high reliability design and implementations (preferred).
  • Good scripting skills in csh/bash, Perl, or Python (preferred).
  • Familiarity with Verilog/SystemVerilog, UPF, formal verification, and DRC rule checking (preferred).

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