ASIC/SOC DFT Engineer

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Austin, TX
Posted
36 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $197k
$143k most similar roles pay here $239k

This listing doesn't post a salary. Most similar roles pay $174,900–$218,875.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · ASIC/SOC DFT Engineer

Role Posting Log in to save

The ASIC/SOC DFT Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role focuses on the design, integration, and verification of Design for Test fabrics and IP within subsystems. Key responsibilities include evaluating design readiness for scan insertion through RTL and physical design tools, refining scan insertion recipes for maximum coverage, and performing ATPG analysis to ensure quality scan chain construction. The engineer will also run gate level simulations, create ATPG content for post-silicon testing, and collaborate with physical design and manufacturing teams. Required skills include experience in scan insertion or DFT setup, proficiency in Verilog/SystemVerilog, and scripting in csh, bash, Perl, or Python. Technical competencies include understanding UPF, formal verification, DRC rule checking, and high reliability design for the Starlink network.

Skills

ASIC DFT Scan Insertion ATPG Verilog SystemVerilog Python Bash Perl UPF Gate Level Simulation SDF RTL Physical Design Formal Verification DRC Synthesis Silicon Engineering

What you'll do

  • Evaluate design readiness for scan insertion using RTL and physical design DRC tools.
  • Integrate and verify Design for Test (DFT) fabrics and IP within subsystems.
  • Run and evaluate scan insertion through synthesis tools to refine recipes for maximum coverage.
  • Perform ATPG analysis to ensure high-quality scan chain construction and meet coverage goals.
  • Run and debug non-timing and SDF annotated gate level simulations.
  • Create and validate ATPG content for use in post-silicon testing via gate level simulation.
  • Coordinate with physical design, ATPG, and manufacturing teams to ensure high quality scan coverage.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 1+ years of professional experience working with ASICs.
  • Experience in scan insertion or DFT setup.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, or asylee (or eligible for such status).
  • Understanding of ASIC design flow, methodologies, physical design, and verification (preferred).
  • Experience with high reliability design and implementations (preferred).
  • Good scripting skills in csh, bash, Perl, or Python (preferred).
  • Familiarity with Verilog/SystemVerilog, UPF, formal verification, and DRC rule checking (preferred).

Related searches

More ASIC jobs ASIC jobs in Austin All jobs at SpaceX

More like this

Similar roles

ASIC/SOC DFT Engineer

SpaceX

Palo Alto, CA 36 days ago $135,000–$175,000
ASIC DFT Scan Insertion ATPG Verilog SystemVerilog Python Bash Perl UPF Gate Level Simulation SDF DRC Formal Verification RTL Physical Design
1+ yrs exp
Save

Senior ASIC DFT Engineer

SpaceX

Irvine, CA 105 days ago $165,000–$260,000
DFT Siemens Tessent ATPG Python Perl Tcl C++ Gate-level Simulation SDF ATE Teradyn Advantest IEEE 1500 IEEE 1149.1 BIST Scan Insertion Post-silicon Validation
5+ yrs exp
Save

Senior ASIC DFT Engineer

SpaceX

Palo Alto, CA 105 days ago $175,000–$280,000
DFT Siemens Tessent ATPG Python Perl Tcl C++ Gate-level Simulation SDF ATE Teradyn Advantest IEEE 1500 IEEE 1149.1 BIST Scan Insertion Post-silicon Validation
5+ yrs exp
Save

Principal DFT Engineer

SpaceX

Austin, TX 43 days ago
DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog Python Perl Tcl RTL UPF Gate Level Simulation SDF Formal Verification ATE
10+ yrs exp
Save

Principal DFT Engineer

SpaceX

Irvine, CA 43 days ago $210,000–$340,000
DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog RTL Python Perl Tcl UPF Formal Verification Gate Level Simulation SDF ATE DRC
10+ yrs exp
Save

Principal DFT Engineer

SpaceX

Palo Alto, CA 43 days ago $220,000–$355,000
DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog RTL Python Perl Tcl UPF Formal Verification Gate Level Simulation SDF ATE
10+ yrs exp
Save