ASIC Design Verification Engineering Leader

Cisco

Confirmed live yesterday High trust
Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$214,100–$309,800 / yr
Posted
38 days ago
Freshness
Confirmed live yesterday
Closes
Oct 20, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $262k
$124k most similar roles pay here $330k

This role pays more than 95% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $262k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineering Leader

As an ASIC Design Verification Engineering Leader, you will join the team to drive next-generation data center solutions by architecting and building cutting-edge verification infrastructure from scratch across block, cluster, and top-level environments. You will ensure maximum functional coverage and elite quality for complex silicon while collaborating with design, emulation, and software teams to debug critical firmware issues and lead hands-on ASIC bring-up. The role requires proficiency in Verilog, SystemVerilog, UVM, and scripting languages like Python or Perl. Preferred skills include experience with Linux, C/C++, Veloce, Palladium, Zebu, HAPS, and formal verification tools like Jasper Gold. You will apply domain expertise in protocols such as PCIe, Ethernet, RDMA, TCP, and Fiber Channel to ensure seamless integration and optimal performance for hardware platforms powering cloud infrastructure.

What you'll do

  • Architect and build cutting-edge design verification infrastructure from scratch across block, cluster, and top-level environments.
  • Ensure maximum functional coverage and high quality for complex silicon designs.
  • Debug critical firmware issues in coordination with design, emulation, and software teams.
  • Lead hands-on ASIC bring-up processes to ensure hardware functionality.
  • Provide technical leadership to guarantee seamless integration and optimal performance for cloud infrastructure platforms.
  • Execute verification for full chip levels or large blocks using Verilog, SystemVerilog, and UVM.
  • Utilize scripting languages like Python or Perl to support design and verification workflows.

What we're looking for

  • Bachelor's degree plus 12 years of experience, Master's plus 8 years, or PhD plus 5 years of related experience.
  • Experience with Verilog, SystemVerilog, and UVM within the last 2-3 years.
  • Experience with scripting languages such as Perl or Python.
  • Experience with ASIC design and verification processes, including debugging, methodology, and tools.
  • Experience verifying blocks, clusters, or full chip levels for ASIC.
  • Preferred experience with Linux, C/C++, and emulation tools like Veloce, Palladium, Zebu, or HAPS.
  • Preferred experience in post-silicon lab bring-up and formal verification using tools like Jasper Gold.
  • Preferred domain expertise in protocols such as PCIe, Ethernet, RDMA, TCP, or Fiber Channel.

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