Senior SOC/ASIC Physical Design Engineer

SpaceX

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Austin, TXIrvine, CASunnyvale, CA
Posted
154 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $202k
$142k $273k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $177,250–$227,500.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Senior SOC/ASIC Physical Design Engineer

Role Posting Log in to save

The Sr. SOC/ASIC Physical Design Engineer joins the Silicon Engineering team to develop next-generation silicon for space and ground infrastructures. This role involves performing partition synthesis and physical implementation steps, including floorplanning, power/ground grid generation, place and route, and various signoff checks like timing, noise, and electromigration. The engineer will develop physical design methodologies, write automation scripts, and collaborate with the ASIC design team on architectural feasibility and RTL tradeoffs. Key technical requirements include experience with RTL2GDSII flows, industry-standard EDA tools, and deep sub-micron FinFET and CMOS solid state physics. Candidates should possess knowledge of CMOS digital design principles, power dissipation, and DFT/Scan/MBIST. The work focuses on expanding the performance and capabilities of the Starlink network to provide global connectivity.

Skills

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route Physical Verification Electromigration Voltage Drop Logic Equivalency FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools

What you'll do

  • Perform partition synthesis and physical implementation steps including floorplanning, place and route, and power/ground grid generation.
  • Execute physical verification, electromigration, voltage drop, and logic equivalency signoff checks.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Conduct architectural feasibility studies to develop timing, power, and area design targets.
  • Resolve design, timing, and congestion issues while identifying and driving technical solutions.
  • Run and debug signoff closure issues in static timing analysis and noise analysis.
  • Explore RTL and design tradeoffs to optimize next-generation silicon for space and ground infrastructure.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of ASIC and/or physical design flow development experience in industry.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows (preferred).
  • Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms (preferred).
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics (preferred).
  • Knowledge of CMOS digital design principles, standard cell functionality, and standard cell libraries (preferred).
  • Good scripting skills in csh/bash, Perl, Python, TCL, or Makefile (preferred).

Related searches

More Sr. SOC jobs Sr. SOC jobs in Austin All jobs at SpaceX

More like this

Similar roles

Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA +2 154 days ago $165,000–$260,000
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
Save

Senior SOC/ASIC Physical Design Engineer

SpaceX

Palo Alto, CA +3 154 days ago $175,000–$280,000
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
Save

Senior ASIC Design Engineer

SpaceX

Austin, TX +3 27 days ago
Verilog System Verilog RTL Design ASIC SoC Synthesis Timing Closure AXI AHB Python HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems Formality Check Silicon Bring-up
5+ yrs exp
Save

Senior ASIC Design Engineer

SpaceX

Irvine, CA +3 27 days ago $165,000–$265,000
Verilog System Verilog RTL Design ASIC SoC Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp
Save

Senior ASIC Design Engineer

SpaceX

Palo Alto, CA +3 18 days ago $175,000–$280,000
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp
Save

Senior ASIC Design Engineer

SpaceX

Redmond, WA +3 27 days ago $165,000–$270,000
RTL Design Verilog System Verilog ASIC SoC Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems
5+ yrs exp
Save