Senior SOC/ASIC Physical Design Engineer

SpaceX

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Austin, TX
Posted
109 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $199k
$144k most similar roles pay here $244k

This listing doesn't post a salary. Most similar roles pay $174,843–$223,700.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Senior SOC/ASIC Physical Design Engineer

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The Sr. SOC/ASIC Physical Design Engineer joins the Silicon Engineering team to develop next-generation silicon for space and ground infrastructure. This role involves performing partition synthesis and physical implementation steps, including floorplanning, power/ground grid generation, place and route, and signoff checks such as static timing analysis, noise, electromigration, and voltage drop. The engineer will also develop automation scripts and collaborate with the ASIC design team to drive architectural feasibility studies and resolve flow issues. Key technical requirements include experience in RTL2GDSII flows, knowledge of deep sub-micron FinFET and CMOS solid state physics, and familiarity with DFT/Scan/MBIST. Proficiency in scripting languages like Python, Perl, TCL, and Bash is required. The role focuses on the hardware components enabling global connectivity through the Starlink satellite network.

Skills

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST FinFET CMOS Python TCL Perl Bash Makefile EDA Tools

What you'll do

  • Perform partition synthesis and physical implementation steps including floorplanning, power/ground grid generation, and place and route.
  • Execute signoff checks for timing, noise, physical verification, electromigration, and voltage drop.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Conduct architectural feasibility studies to establish timing, power, and area design targets.
  • Resolve complex design, timing, and congestion issues while identifying and driving technical solutions.
  • Debug and fix signoff closure issues in static timing analysis and logic equivalency.
  • Explore RTL and design tradeoffs to optimize chip performance and functionality.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of experience in ASIC and/or physical design flow development.
  • Experience with ASIC/SOC RTL2GDSII physical design and signoff flows.
  • Proficiency with industry standard EDA tools and understanding of their underlying algorithms.
  • Knowledge of deep sub-micron FinFET, CMOS solid state physics, and digital design principles.
  • Understanding of CMOS power dissipation in deep submicron processes and familiarity with CMOS analog circuit design.
  • Knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows.
  • Proficiency in scripting languages such as csh, bash, Perl, Python, TCL, or Makefile.

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