Senior ASIC Design Verification Engineer

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$165,000–$260,000 / yr
Posted
59 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $212k
$137k most similar roles pay here $273k

This role pays more than 68% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $212k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer

Sr. ASIC Design Verification Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role focuses on digital ASIC verification at both the block and system levels, where the engineer will write and review test plans, develop test harnesses and sequences, and execute regressions to achieve code and functional coverage closure. The position involves critical pre-silicon verification, chip bring-up, and post-silicon validation for hardware supporting global connectivity. Key technical requirements include expertise in UVM, OVM, or VMM methodologies, strong object-oriented programming knowledge, and experience with constrained random verification. Candidates should possess skills in scripting languages like Python for automation, along with RTL design capabilities. The work addresses the technical challenge of building reliable, high-performance hardware components to expand the functionality and performance of a global satellite network.

What you'll do

  • Perform digital ASIC verification at both the block and system levels.
  • Write and review comprehensive test plans for complex digital designs.
  • Develop test harnesses and automated test sequences.
  • Execute test plans, run regressions, and achieve code and functional coverage closure.
  • Contribute to pre-silicon verification activities for next-generation ASICs.
  • Participate in chip bring-up and post-silicon validation processes.
  • Utilize UVM/OVM/VMM methodologies and constrained random verification techniques.
  • Develop scripts using Python or other languages to automate verification tasks.

What we're looking for

  • Bachelor's degree in electrical engineering or computer engineering.
  • 5+ years of experience with design verification and test bench development.
  • Experience with verification methodologies such as UVM, OVM, or VMM.
  • Strong object-oriented programming knowledge and coding skills.
  • Experience in constrained random verification.
  • Expertise in developing test plans, implementing coverage models, and analyzing results.
  • Experience with scripting languages like Python for automation.
  • Must be a U.S. citizen, permanent resident, or eligible for required export control authorizations.

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