ASIC Package Engineering Co-op/Intern

Amd

Confirmed live today Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CASanta Clara, CA
Salary
$64,064–$96,096 / yr
Employment
Intern
Posted
63 days ago
Freshness
Confirmed live today
Closes
Aug 25, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $164k
This role $80k
$46k $236k
below market most similar roles pay here above market

This role pays less than 92% of similar roles. Most pay $115,000–$214,000 — the blue band above. At the midpoint, this role pays about $80k versus about $164k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · ASIC Package Engineering Co-op/Intern

The 2027 Undergrad ASIC Package Engineering Co-op/Intern will join the engineering team to help bring advanced packaging technology to reality. In this role, the student will support Package design and Package Development Engineers by prioritizing and optimizing new projects. Day-to-day responsibilities include completing substrate, interposer, and bump designs for products, test vehicles, and probe card substrates. The intern will also perform design verification implementation to ensure performance, quality, and efficiency while analyzing yield and defect metrics. Key tasks involve evaluating and benchmarking packaging materials to achieve cost-efficient designs. Required skills and knowledge include transmission lines, electric circuits, semiconductor theory, and packaging processes. Candidates should possess experience with package, silicon, or PCB design software, scripting languages like Perl, Python, or SQL, and data visualization tools like powerBI.

What you'll do

  • Support Package design and Development Engineers in prioritizing and optimizing new projects.
  • Complete substrate, interposer, and bump designs for AMD products and test vehicles.
  • Implement design verification projects to ensure product performance, quality, and efficiency.
  • Analyze yield and defect metrics to improve overall design performance.
  • Evaluate and benchmark packaging materials to achieve cost-efficient designs.
  • Interact with partners to meet specific performance and yield requirements.

What we're looking for

  • You must be currently enrolled in a US-based university in a Bachelor's degree program.
  • Your major must be Electrical Engineering, Engineering Science, Computer Engineering, Mechanical Engineering, Material Science Engineering, or a related field.
  • You must be able to work full-time (40 hours a week) in a hybrid or onsite structure in San Jose or Santa Clara.
  • Knowledge of transmission lines and electric circuits is encouraged (preferred).
  • Experience with package, silicon, or PCB design software is encouraged (preferred).
  • Proficiency in scripting languages such as Perl, Python, or SQL is encouraged (preferred).
  • Knowledge of semiconductor theory and packaging process/technology is encouraged (preferred).
  • Experience with data analytics and visualization tools like PowerBI is encouraged (preferred).

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