Senior Manager, ASIC Chip Engineering

Nvidia

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $232,000–$368,000 / yr
Employment: Full-time
Posted: 82 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k

This role $300k

$138k $393k

below market most similar roles pay here above market

This role pays more than 97% of similar roles. Most pay $177,250–$227,500 — the blue band above. At the midpoint, this role pays about $300k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior Manager, ASIC Chip Engineering

Role Posting Log in to save

The Senior Manager, ASIC Chip Engineering joins a dynamic team to drive the development of future SoC processors for client, workstation, embedded, and automotive markets. This role involves managing the execution of SOCs from concept to production, defining project achievements, and coordinating activities across multi-functional teams including IP design, integration, DFT, physical design, VLSI, emulation, software, and operations. The manager must identify technical risks, provide technical leadership, and ensure successful productization with first silicon. Key requirements include deep knowledge of chip life cycle phases, including front-end flows like RTL coding and verification, and back-end flows like physical design and clock distribution. Candidates should possess skills in data analytics, automation flows using various programming languages, and experience with graphics processing, memory, and I/O sub-systems.

Skills

SoC VLSI RTL DFT Physical Design Emulation Silicon Bring-up Micro-architecture Low-power Design ISO26262 Data Analytics Automation Algorithm Development Verification

What you'll do

Drive the execution of SoCs from initial concept through to final production.
Define and track project achievements and dependencies across multi-functional engineering teams.
Coordinate activities for IP design, integration, DFT, physical design, VLSI, emulation, and software teams.
Identify and characterize key technical risks and develop mitigation strategies with engineering management.
Provide technical leadership to the team to ensure successful productization with first silicon.
Present complex project progress to stakeholders using key performance indicators and risk assessments.
Implement data analytics and automation flows to improve execution efficiency across the organization.
Lead after-action reviews to identify and deploy creative solutions for continuous workflow improvement.

What we're looking for

BSEE or equivalent experience is required.
MSEE or MSCE is preferred.
Minimum of 10 overall years of proven experience in chip development is required.
Minimum of 5+ years managing an SoC or a key sub-system is required.
Experience in development cycle of graphics processing, memory, and I/O sub-systems in SOC chips is required.
Deep knowledge of the entire chip life cycle from concept to production is required.
Ability to multi-task across simultaneous projects and drive resolution of complex technical issues in a matrixed team is required.
Strong algorithm development and programming skills are preferred.

Similar roles

Manager, ASIC Chip - GPU

Nvidia

Santa Clara, CA 82 days ago $196,000–$310,500

ASIC GPU SoC RTL VLSI DFT Silicon Process Technology Front-end Design Flow Micro-architecture Design Verification Performance Modeling Power Budgeting Yield Analysis Emulation System Design AI Datacenter Products

10+ yrs exp

Save

Manager, Chip Software

Nvidia

Santa Clara, CA 78 days ago $184,000–$287,500

SOC Embedded Systems Software Development Life Cycle Pre-Silicon Post-Silicon Bring-up Kernel System Software Device Drivers Operating Systems Simulation Emulation ISO26262 Safety Standards CPU Memory Buses Interconnects

10+ yrs exp

Save

Senior Chip Lead Engineer, SoC/ASIC

Amd

San Jose, CA 54 days ago $164,000–$246,000

ASIC FPGA Verilog SystemVerilog VHDL RTL Design DFT Physical Design Timing Closure Power Optimization EDA Tools Silicon Validation Device Drivers System Software AI/ML Accelerators CPU GPU

10+ yrs exp

Save

Senior ASIC Engineer

Cisco

San Jose, CA 53 days ago $167,700–$245,200

ASIC Design System Verilog UVM Post-silicon Lab Bring-up C/C++ Python Perl Linux Veloce Palladium Zebu HAPS Networking

7+ yrs exp

Save

Manager, ASIC Design Engineering

SpaceX

Hawthorne, CA 179 days ago $190,000–$245,000

ASIC Design FPGA Verilog System Verilog RTL Synthesis Timing Closure Python TCL VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II AXI AHB DSP RFIC Embedded Processors

5+ yrs exp

Save

Senior ASIC Hardware Design Engineer

Nvidia

Westford, MA 117 days ago

Verilog SystemVerilog RTL ASIC Design VLSI Python Perl Micro-architecture Logic Design Timing Closure Synthesis Digital Systems Hardware Engineering

5+ yrs exp

Save