Senior Manager, ASIC Chip Engineering

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $232,000–$368,000 / yr
Posted: 36 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k

This role $300k

$134k most similar roles pay here $393k

This role pays more than 98% of similar roles. Most pay $177,250–$227,500 — the shaded band above. At the midpoint, this role pays about $300k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Manager, ASIC Chip Engineering

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As a Senior Manager, ASIC Chip Engineering, you will join a dynamic team to drive the development of future SoC processors for client, workstation, embedded, and automotive markets. You are responsible for executing SOCs from concept to production by defining and tracking project achievements across multi-functional teams including IP design, integration, DFT, physical design, VLSI, emulation, software, and operation teams. The role involves identifying technical risks, providing leadership in a matrixed environment, and implementing data analytics and automation flows using various programming languages to improve execution efficiency. You will manage the entire chip life cycle, encompassing front-end flows like micro-architecture and RTL coding, as well as back-end flows including physical design and silicon bring-up. Key technical areas include graphics processing, memory, and I/O sub-systems, with specific focus on safety standards like ISO26262.

Skills

SoC VLSI RTL DFT Physical Design Emulation Silicon Bring-up Low-power Design Data Analytics Automation ISO26262 Algorithm Development

What you'll do

Drive the execution of SoCs from initial concept through to final production.
Track project achievements and dependencies across multi-functional engineering teams.
Coordinate activities for IP design, integration, DFT, physical design, VLSI, emulation, and software teams.
Identify and characterize key technical risks while developing mitigation strategies with management.
Provide technical leadership to the team to ensure successful productization with first silicon.
Present progress of complex efforts using key performance indicators and risk analysis.
Implement data analytics and automation flows to improve execution efficiency across organizations.
Conduct after-action reviews to identify and deploy creative solutions for project workflow improvements.

What we're looking for

BSEE degree required (MSEE/MSCE preferred).
Experience in chip development.
At least 5 years of experience managing an SoC or a key sub-system.
Experience in the development cycle of graphics processing, memory, and I/O sub-systems in SOC chips.
Deep knowledge of the entire chip life cycle from concept to production including front-end, back-end, and silicon bring-up.
Ability to multi-task across simultaneous projects and resolve complex technical issues in a matrixed team.
Excellent written, verbal, and technical communication skills.
Strong algorithm development and programming skills (preferred); experience with ISO26262 safety standards (preferred).

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