ASIC/SOC DFT Engineer

SpaceX

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Palo Alto, CA
Salary
$135,000–$175,000 / yr
Posted
36 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $155k
$123k most similar roles pay here $244k

This role pays less than 85% of similar roles. Most pay $175,000–$223,175 — the shaded band above. At the midpoint, this role pays about $155k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · ASIC/SOC DFT Engineer

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The ASIC/SOC DFT Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role focuses on the design, integration, and verification of Design for Test fabrics and IP within subsystems. Key responsibilities include evaluating design readiness for scan insertion through RTL and physical design tools, refining scan insertion recipes for maximum coverage, and performing ATPG analysis to ensure high-quality scan chain construction. The engineer will also run gate level simulations, create ATPG content for post-silicon testing, and collaborate with manufacturing teams. Required skills include experience in scan insertion or DFT setup, proficiency in Verilog/SystemVerilog, and scripting in languages like Python, Perl, or Bash. Additional technical competencies include familiarity with UPF, formal verification, DRC rule checking, and high reliability design for the Starlink network.

Skills

ASIC DFT Scan Insertion ATPG Verilog SystemVerilog Python Bash Perl UPF Gate Level Simulation SDF DRC Formal Verification RTL Physical Design

What you'll do

  • Evaluate design readiness for scan insertion through RTL and physical design DRC tools.
  • Integrate and verify Design for Test (DFT) fabrics and IP within subsystems.
  • Run and evaluate scan insertion through synthesis tools to refine recipes for maximum coverage.
  • Perform ATPG analysis to ensure high-quality scan chain construction and meet coverage goals.
  • Create and validate ATPG content for post-silicon testing using gate level simulations.
  • Debug non-timing and SDF annotated gate level simulations.
  • Coordinate with physical design, ATPG, and manufacturing teams to ensure high quality scan coverage in silicon.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • At least 1 year of professional experience working with ASICs.
  • Experience in scan insertion or DFT setup.
  • Understanding of ASIC design flow, methodologies, physical design, and verification.
  • Proficiency in scripting languages such as csh, bash, Perl, or Python.
  • Familiarity with Verilog/SystemVerilog for implementation or integration of design blocks.
  • Knowledge of UPF, formal verification, and DRC rule checking.
  • Must be a U.S. citizen, permanent resident, or eligible for required export control authorizations.

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