ASIC/SOC DFT Engineer

SpaceX

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Palo Alto, CAAustin, TX
Salary
$135,000–$175,000 / yr
Posted
82 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $202k
This role $155k
$121k $263k
below market most similar roles pay here above market

This role pays less than 88% of similar roles. Most pay $177,250–$227,350 — the blue band above. At the midpoint, this role pays about $155k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · ASIC/SOC DFT Engineer

Role Posting Log in to save

The ASIC/SOC DFT Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructures. This role focuses on enabling global connectivity by expanding the performance and capabilities of the Starlink network. Key responsibilities include evaluating design readiness for scan insertion using RTL and physical design Scan Design Rule Check tools, integrating DFT fabrics and IP within subsystems, and refining scan insertion recipes for maximum coverage. You will run ATPG analysis, debug non-timing and SDF annotated gate level simulations, and create ATPG content for post-silicon testing. Required skills include experience with ASICs, scan insertion, and DFT setup. Preferred qualifications include proficiency in Verilog/SystemVerilog, Python, Perl, and Bash, along with knowledge of UPF, formal verification, and high reliability design.

Skills

ASIC SOC DFT ATPG Verilog SystemVerilog Python Perl Bash csh UPF DRC RTL Gate Level Simulation SDF Formal Verification Synthesis Physical Design

What you'll do

  • Evaluate design readiness for scan insertion using RTL and physical design DRC tools.
  • Integrate and verify Design for Test (DFT) fabrics and IP within subsystems.
  • Run scan insertion through synthesis tools and refine recipes to maximize coverage.
  • Perform ATPG analysis to ensure quality scan chain construction and meet coverage goals.
  • Run and debug non-timing and SDF annotated gate level simulations.
  • Create and validate ATPG content for post-silicon testing using gate level simulation.
  • Coordinate with physical design and manufacturing teams to achieve high-quality scan coverage in silicon.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 1+ years of professional experience working with ASICs.
  • Experience in scan insertion or DFT setup.
  • Understanding of ASIC design flow, methodologies, physical design, and verification (preferred).
  • Experience with high reliability design and implementations (preferred).
  • Good scripting skills in csh/bash, Perl, or Python (preferred).
  • Familiarity with Verilog/SystemVerilog, UPF, formal verification, and DRC rule checking (preferred).
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.

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