Senior SOC/ASIC Physical Design Engineer

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$165,000–$260,000 / yr
Posted
108 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k
This role $212k
$140k most similar roles pay here $273k

This role pays more than 61% of similar roles. Most pay $173,906–$223,700 — the shaded band above. At the midpoint, this role pays about $212k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Senior SOC/ASIC Physical Design Engineer

Role Posting Log in to save

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation silicon for space and ground infrastructure. The role involves performing partition synthesis and physical implementation steps, including floorplanning, power/ground grid generation, place and route, and signoff checks such as static timing analysis, electromigration, and voltage drop. You will also develop automation scripts, conduct architectural feasibility studies, and resolve design or congestion issues to meet performance targets. Key technical requirements include experience with RTL2GDSII flows, industry-standard EDA tools, and deep sub-micron FinFET and CMOS solid state physics. Candidates should possess knowledge of DFT/Scan/MBIST, standard cell libraries, and scripting in languages like Python, Perl, TCL, or Bash. This position focuses on creating advanced chips to enable reliable global connectivity through the Starlink network's hardware infrastructure.

Skills

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis

What you'll do

  • Perform partition synthesis and physical implementation steps including floorplanning, power/ground grid generation, and place and route.
  • Execute signoff checks for timing, noise, physical verification, electromigration, voltage drop, and logic equivalency.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Conduct architectural feasibility studies with the ASIC design team to establish timing, power, and area targets.
  • Resolve complex design, timing, and congestion issues while identifying and driving technical solutions.
  • Debug and fix signoff closure issues in static timing analysis (STA) and physical verification flows.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of experience in ASIC and/or physical design flow development.
  • Experience with ASIC/SOC RTL2GDSII physical design and signoff flows.
  • Proficiency with industry standard EDA tools and their underlying algorithms.
  • Knowledge of deep sub-micron FinFET, CMOS solid state physics, and digital design principles.
  • Understanding of CMOS power dissipation in deep submicron processes and analog circuit design.
  • Familiarity with DFT/Scan/MBIST/LBIST impacts on physical design flows.
  • Proficiency in scripting languages such as csh, bash, Perl, Python, TCL, or Makefile.

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