Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $160,000–$220,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $188k

This role $190k

$152k most similar roles pay here $233k

This role pays less than 55% of similar roles. Most pay $160,000–$216,250 — the shaded band above. At the midpoint, this role pays about $190k versus about $188k for comparable roles.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

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As a Sr. SOC/ASIC Physical Design Engineer in the Silicon Engineering team, you will lead the physical design and signoff flows for complex ASIC/SOC projects, leveraging industry-standard EDA tools to ensure high-quality RTL2GDSII designs. Your daily tasks include optimizing CMOS digital circuits, integrating DFT/Scan/LBIST features, and collaborating with cross-functional teams to address intricate physical design challenges. Ideal candidates possess deep knowledge of standard cell libraries and the underlying algorithms of EDA tools, along with a strong background in CMOS digital design principles. This role demands expertise in scripting languages like Perl or Python for automation and an understanding of large-scale semiconductor manufacturing processes.

Skills

EDA RTL2GDSII ASIC SOC CMOS DFT Scan MBIST LBIST Standard Cells Physical Design Flows

What you'll do

Perform ASIC/SOC RTL2GDSII physical design and signoff flows.
Utilize industry-standard EDA tools for efficient design implementation.
Apply CMOS digital design principles in creating standard cell libraries.
Implement DFT/Scan/LBIST techniques to enhance testability of designs.
Ensure understanding and compliance with ITAR requirements.

What we're looking for

Strong experience in ASIC/SOC physical design and signoff flows.
Proficiency with industry-standard EDA tools and understanding of their algorithms.
Knowledge of CMOS digital design principles and standard cell libraries.
Understanding of DFT/Scan/MBIST/LBIST impacts on physical design flows.
ITAR compliance for U.S. Department of State requirements.

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