Senior Custom ASIC Engineering Lead

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CAFort Collins, COIrvine, CA
Salary
$143,800–$230,000 / yr
Posted
84 days ago
Freshness
Confirmed live yesterday
Closes
Dec 16, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $187k
$133k most similar roles pay here $246k

This role pays less than 55% of similar roles. Most pay $175,000–$227,300 — the shaded band above. At the midpoint, this role pays about $187k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Senior Custom ASIC Engineering Lead

Role Posting Log in to save

The Senior Custom ASIC Engineering Lead joins the ASIC Products Division to guide customer teams designing complex chips for AI, HPC, networking, and storage. This role involves managing external customer programs from inception through production, including RFQs, design, test, packaging, and fabrication. You will advise customers on EDA flows and design methodologies while proactively identifying risks to ensure tape-out quality standards are met. The position requires expertise in physical design, STA, DFT, and low power management across advanced technology nodes. Candidates must be proficient in TCL, shell, and scripting languages. Preferred skills include experience with SERDES protocols, Verilog RTL coding, logic synthesis, and memory BIST. You will bridge the gap between technical deep-dives with engineers and high-level summaries for management to solve critical infrastructure challenges within the semiconductor industry.

Skills

Physical Design STA DFT EDA Tools TCL Verilog RTL Logic Synthesis SERDES Low Power Design Packaging Tape-out DRC Scan Memory BIST Microarchitecture

What you'll do

  • Manage external customer ASIC programs from inception through fabrication, bring-up, and production.
  • Advise customers on best practices regarding EDA tools, design flows, and methodologies.
  • Proactively identify risks to design quality and project schedules to execute mitigation actions.
  • Execute physical design flows to ensure customer netlists meet strict tape-out quality standards.
  • Analyze PPA tradeoffs across various library components and architectures for advanced technology nodes.
  • Provide technical deep-dives with engineers and high-level summaries for management.
  • Participate in cross-functional discussions regarding chip marketing, sales, and regulatory compliance.

What we're looking for

  • Bachelor's degree and 12+ years of related experience, or a Master's degree and 10+ years of related experience.
  • Proven experience with multiple tape-outs in advanced technology nodes.
  • Expertise in physical design, STA, DFT, and packaging.
  • Ability to analyze PPA tradeoffs across various library components and architectures.
  • Knowledge of low power design and power management.
  • Proficiency in EDA tools, design flows for physical design, logic simulation, test, and packaging.
  • Programming skills in TCL, shell, and other scripting languages.
  • Experience with SERDES communications protocols, Verilog RTL coding, and DFT methods is preferred.

Related searches

More Senior Custom ASIC Engineering Lead jobs Senior Custom ASIC Engineering Lead jobs in San Jose All jobs at Broadcom

More like this

Similar roles

Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA +2 84 days ago $143,800–$230,000
Physical Design STA DFT TCL Verilog RTL Logic Synthesis SERDES Low Power Design EDA Tools Tape-out Packaging Logic Simulation DRC Memory BIST
10+ yrs exp
Save

Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA 43 days ago $143,800–$230,000
Physical Design STA DFT EDA Tools TCL Verilog RTL Logic Synthesis Low Power Design SERDES DRC Scan Memory BIST Chip Architecture Packaging Tape-out
10+ yrs exp
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 46 days ago $136,000–$218,500
ASIC Design Verilog System-Verilog RTL VLSI Digital Design Synthesis Timing Analysis CDC Formal Equivalence Python Perl Tcl Make files DFT mixed signal Post-Si Bringup Agentic AI
3+ yrs exp Hybrid
Save

Lead ASIC Digital Design Engineer

General Dynamics

Sudbury, MA +4 9 days ago $176,512–$187,000
RTL Design ASIC FPGA Microarchitecture Synthesis Static Timing Analysis Clock Domain Crossing CDC Tape-out FinFET EDA Tools JIRA Power Analysis Bus Fabric Formal Verification Physical Verification Microsoft Office
8+ yrs exp Hybrid
Save

ASIC Implementation Engineer

Broadcom

San Jose, CA 137 days ago $120,000–$192,000
Physical Design STA Floorplanning Layout Clock Tree Synthesis EM/IR Analysis TCL Perl EDA Tools RTL Tape-out
8+ yrs exp
Save

Senior Chip Lead Engineer SoC/ASIC

Amd

San Jose, CA 8 days ago $164,000–$246,000
ASIC FPGA RTL Verilog SystemVerilog VHDL EDA Tools Physical Design Timing Closure Power Optimization DFT Silicon Validation Device Drivers Low-level Software AI/ML Accelerators
10+ yrs exp
Save