Senior Custom ASIC Engineering Lead

Broadcom

Quick summary

Work type
On-site
Location
San Jose, CAFort Collins, COIrvine, CA
Salary
$143,800–$230,000 / yr
Posted
9 days ago
Closes
Dec 16, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k
This role $187k
$133k most similar roles pay here $240k

This role pays less than 52% of similar roles. Most pay $175,000–$216,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 95 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 93 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Senior Custom ASIC Engineering Lead

As a senior engineer in Broadcom’s ASIC Products Division, you will lead external and internal cross-functional teams through the entire lifecycle of complex chip designs for AI, HPC, networking, and storage. Your responsibilities include managing customer programs from RFQ to production, advising on EDA best practices, identifying and mitigating design risks, executing physical design flows, and collaborating with marketing, sales, legal, and regulatory teams. You must have extensive experience in multiple tape-outs at advanced technology nodes, analyzing PPA tradeoffs, low power design, and hands-on expertise in physical design, STA, EDA tools, and scripting languages like TCL and shell. Knowledge of DFT methods is a plus, as you will work closely with customers to ensure high-quality designs that meet stringent standards.

What you'll do

  • Manage external customer ASIC programs from inception to finish.
  • Advise customers on best practices in EDA, flows, and design methodologies.
  • Proactively assess potential risks to the design quality and project schedule.
  • Execute physical design flows to ensure tape-out quality standards are met.
  • Stay abreast of developments in Broadcom IPs, technology, and end-user applications.

What we're looking for

  • Extensive experience in multiple tape-outs at advanced technology nodes.
  • Proficiency in physical design, STA, EDA tools, and scripting languages like TCL and shell.
  • Expertise in analyzing PPA tradeoffs among library components and architectures.
  • Strong knowledge of low power design and power management techniques.
  • Ability to manage external customer ASIC programs from inception to production.
  • Hands-on experience with DFT methods including scan, memory BIST, and repair.

More like this

Similar roles

Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA +2 9 days ago $143,800$230,000
TCL Shell Scripting EDA tools Physical design STA DFT Verilog RTL coding Logic simulation Test Packaging Low power design Power management SERDES DRC Logic synthesis Memory BIST Microarchitecture Chip architecture

Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA +2 9 days ago $143,800$230,000
TCL Shell Scripting EDA tools Physical design STA DFT Verilog RTL coding Logic simulation Test Packaging Low power design Power management SERDES DRC Logic synthesis Memory BIST Microarchitecture Chip architecture

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 48 days ago $136,000$218,500
Verilog System-Verilog Perl Python Tcl Makefiles RTL CDC checks Formal equivalence Timing analysis DFT ATE test development Post-si bringup Debugging Behavioral real number modeling Mixed signal design Custom designed IPs Agentic AI flows
Hybrid

Principal CPU Physical Design Engineer

Qualcomm

San Diego, CA 18 days ago $211,900$317,900
TCL Python Synopsys Cadence RTL-to-GDSII ASIC SoC Physical Design Timing Closure Power Optimization EDA STA Signoff Place & Route Scripting Advanced Nodes PPA Trade-offs CPU Design Challenges Data-Driven Debugging

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 39 days ago $168,000$264,500
Verilog System-Verilog RTL ASIC Logic Design Computer Architecture Digital Systems Verification Logic Synthesis Timing Analysis ECO Post Silicon Debug Arbiters Scheduling Synchronization Bus Protocols Interconnect Networks Switches Virtual Channels

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 110 days ago $168,000$264,500
Verilog RTL C C++ Python Perl VLSI Computer_Architecture Digital_Systems Logic_Synthesis Timing_Analysis CI/CD
Hybrid