Senior Custom ASIC Engineering Lead

Broadcom

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Jose, CAFort Collins, COIrvine, CA
Salary
$143,800–$230,000 / yr
Employment
Full-time
Posted
130 days ago
Freshness
Confirmed live today
Closes
Dec 16, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k
This role $187k
$132k $257k
below market most similar roles pay here above market

This role pays less than 59% of similar roles. Most pay $177,250–$222,625 — the blue band above. At the midpoint, this role pays about $187k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Senior Custom ASIC Engineering Lead

Role Posting Log in to save

The Senior Custom ASIC Engineering Lead joins the ASIC Products Division to guide customer teams designing challenging chips for AI, HPC, networking, and storage. This role involves managing external customer ASIC programs from inception to production, including RFQs, design, test, packaging, and fabrication. You will advise customers on best practices in EDA flows and design methodologies while proactively assessing risks to design quality and project schedules. Key responsibilities include executing physical design flows to ensure tape-in netlists meet stringent quality standards. Required skills include multiple tape-outs in advanced technology nodes, PPA tradeoff analysis, low power design, and hands-on experience in physical design, STA, and logic simulation. You must be proficient in TCL, shell, and scripting languages to support these complex semiconductor infrastructure projects.

Skills

Physical Design STA DFT TCL Verilog EDA Tools Logic Synthesis DRC SERDES Logic Simulation Power Management Scan Memory BIST Chip Architecture

What you'll do

  • Manage external customer ASIC programs from inception through production.
  • Advise customers on best practices for EDA flows and design methodologies.
  • Proactively assess design quality risks and execute mitigation actions with cross-functional teams.
  • Execute physical design flows to verify that customer netlists meet tape-out quality standards.
  • Analyze PPA tradeoffs among various library components and architectures.
  • Participate in chip discussions with marketing, sales, legal, and regulatory compliance teams.
  • Stay updated on developments in Broadcom IPs, technology, and end-user applications.

What we're looking for

  • Bachelor's degree and 12+ years of related experience; or Master's degree and 10+ years of related experience.
  • Proven experience with multiple tape-outs in advanced technology nodes.
  • Knowledgeable in low power design and power management.
  • Hands-on experience in physical design, STA, EDA tools, design flows, logic simulation, test, and packaging.
  • Programming skills in TCL, shell, and scripting languages.
  • Ability to analyze PPA tradeoffs involved amongst various library components and architectures.
  • Exposure to SERDES communications protocols (preferred).
  • Knowledge of logic design, chip architecture, microarchitecture, Verilog RTL coding, and DFT methods (preferred).

Related searches

More Senior Custom ASIC Engineering Lead jobs Senior Custom ASIC Engineering Lead jobs in San Jose All jobs at Broadcom

More like this

Similar roles

Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA +2 130 days ago $143,800–$230,000
Physical Design STA DFT Packaging EDA Tools TCL Verilog RTL Logic Synthesis DRC SERDES Scan Memory BIST Logic Simulation Low Power Design
10+ yrs exp
Save

Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA 89 days ago $143,800–$230,000
Physical Design STA DFT TCL Verilog Logic Synthesis DRC SERDES Logic Simulation Power Management Memory BIST Scan Packaging Tape-out EDA Tools
10+ yrs exp
Save

Senior Chip Lead Engineer, SoC/ASIC

Amd

San Jose, CA 54 days ago $164,000–$246,000
ASIC FPGA Verilog SystemVerilog VHDL RTL Design DFT Physical Design Timing Closure Power Optimization EDA Tools Silicon Validation Device Drivers System Software AI/ML Accelerators CPU GPU
10+ yrs exp
Save

Senior ASIC Engineer

Cisco

San Jose, CA 53 days ago $167,700–$245,200
ASIC Design System Verilog UVM Post-silicon Lab Bring-up C/C++ Python Perl Linux Veloce Palladium Zebu HAPS Networking
7+ yrs exp
Save

ASIC Engineering Technical Leader

Cisco

San Jose, CA 28 days ago $186,900–$267,700
ASIC VLSI SOC DFT Scan ATPG JTAG MBIST PVT SerDes Advantest 93000 JMP SRAM Characterization Qualification Yield Improvement
9+ yrs exp Hybrid
Save