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Active Keyword: ASIC Design Engineer Remove filter Clear all

20 of up to 20 (filtered)

ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm

San Diego, CA 3 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Posted this week High trust Below market
RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII
4+ yrs exp
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ASIC Design Engineer, Tools and Methodology Development

Nvidia

Austin, TX 3 days ago $116,000–$189,750
Actively hiring Confirmed live yesterday Posted this week High trust Below market
Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation DevOps Synthesis CDC Digital Design Hardware Design
3+ yrs exp Hybrid
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ASIC Design Verification Engineer

Cisco

San Jose, CA 3 days ago $167,700–$245,200
Actively hiring Confirmed live 2 days ago Posted this week High trust Competitive pay
System Verilog UVM ASIC Verification Python Perl C C++ Emulation Formal Verification SoC Architecture Silicon Bring-up Post-Silicon Debug
7+ yrs exp
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Senior Staff ASIC Design Engineer

Amd

San Jose, CA 7 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday Posted this week High trust Above market
Verilog System Verilog DFT ATPG RTL Design UVM OVM Python Tcl Perl Shell Synopsys DC Compiler PrimeTime Cadence Virtuoso VCS Static Timing Analysis FPGA HBM PCIe SerDes
Hybrid
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Senior ASIC Design Engineer, DFX

Nvidia

Santa Clara, CA 7 days ago $168,000–$264,500
Actively hiring Confirmed live 2 days ago Posted this week High trust Above market
DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Power Optimization Fuse Controller Verification Synthesis
8+ yrs exp
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High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 8 days ago $140,000–$229,800
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture
4+ yrs exp
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Lead ASIC Digital Design Engineer

General Dynamics

Sudbury, MA +4 8 days ago $176,512–$187,000
Actively hiring Confirmed live yesterday High trust Competitive pay
RTL Design ASIC FPGA Microarchitecture Synthesis Static Timing Analysis Clock Domain Crossing CDC Tape-out FinFET EDA Tools JIRA Power Analysis Bus Fabric Formal Verification Physical Verification Microsoft Office
8+ yrs exp Hybrid
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ASIC Design Engineer, Pixel IP

Apple Inc

Sunnyvale, CA 9 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
RTL Design AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification ASIC Design
10+ yrs exp
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ASIC Design Engineer, Pixel IP

Apple Inc

Sunnyvale, CA 9 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago High trust Above market
RTL AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification ASIC Design
3+ yrs exp
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Senior ASIC Design Engineer, Clocks IP

Nvidia

Santa Clara, CA +1 9 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting
3+ yrs exp Hybrid
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Senior ASIC Design Engineer

Nvidia

Remote (Santa Clara, CA) 9 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design RTL Design SoC Integration Logic Synthesis Timing Analysis Python Perl C++ UCIe Digital Design Verification Methodology Memory Controllers DMA Boot Controllers Fuse Controllers
5+ yrs exp Remote Hybrid
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ASIC Design Engineer, Hardware

Nvidia

Austin, TX 9 days ago $116,000–$189,750
Actively hiring Confirmed live yesterday High trust Below market
RTL Verilog SystemVerilog Python Perl SoC CDC Synthesis VCS GDB Debussy dc_shell DFT Microarchitecture Scripting Silicon Debug Physical Design
2+ yrs exp Hybrid
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ASIC Floorplan Design Engineer

Nvidia

Santa Clara, CA 11 days ago $116,000–$189,750
Actively hiring Confirmed live 2 days ago High trust Below market
ASIC Floorplan VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design Timing Closure Clock Distribution Packaging
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ASIC Design Engineer

Apple Inc

Sunnyvale, CA 14 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
Verilog System Verilog RTL ASIC Design SoC Digital Signal Processing Synthesis Power-Gating AMBA AXI AHB APB Python Perl TCL Linting CDC RDC
10+ yrs exp
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ASIC Design Engineer

Apple Inc

Sunnyvale, CA 14 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday High trust Above market
Verilog System Verilog RTL ASIC SoC Digital Signal Processing AMBA AXI AHB APB Python Perl TCL Synthesis power-gating CDC RDC
5+ yrs exp
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ASIC Design Engineer

Apple Inc

Sunnyvale, CA 14 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Trusted Below market
Verilog System Verilog RTL ASIC Design Digital Signal Processing AMBA AXI AHB APB Synthesis Python Perl TCL SystemC C++ Finite State Machines Pipelining High-Level Synthesis
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AI-Driven ASIC Physical Design Principal Engineer

Cisco

Remote (San Jose, CA) 18 days ago $250,600–$362,600
Actively hiring Confirmed live 2 days ago High trust Above market
Python Claude Innovus ICC2 Calibre Tcl Docker OpenAI API Pinecone Weaviate RAG LLM MLPD STA DRC EDA Tools Vector Databases
10+ yrs exp Remote
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Senior Design Verification Engineer

Qualcomm

San Diego, CA 21 days ago $115,600–$173,400
Actively hiring Confirmed live yesterday Trusted Below market
SystemVerilog UVM Verilog VHDL Python C++ Perl Formal Verification UPF AMBA AXI AHB APB RTL Object-Oriented Programming Scripting Automation
2+ yrs exp
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ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 22 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog SystemVerilog ASIC Design Synthesis Timing Closure CDC RDC UPF AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist Hardware Security
10+ yrs exp
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ASIC Design Engineer, IP Integration & Implementation

Apple Inc

Sunnyvale, CA 22 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Above market
RTL ASIC Design AMBA AXI AHB APB UPF Python Perl TCL Logic Synthesis Static Timing Analysis Formal Verification Floorplanning Timing Closure Low-Power Design
3+ yrs exp
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