Senior ASIC Design Engineer, Memory Subsystem

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
3 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k
This role $177k
$124k $247k
below market most similar roles pay here above market

This role pays less than 60% of similar roles. Most pay $169,500–$217,600 — the blue band above. At the midpoint, this role pays about $177k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1531 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1104 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer, Memory Subsystem

Role Posting Log in to save

The Senior ASIC Design Engineer - Memory Subsystem will join the Memory Subsystem Design team to deliver world-class solutions for sophisticated SOC interconnects, ordering controllers, and memory accelerators. The role involves collaborating with architects, design verification, formal verification, and physical design teams to address complex area, latency, power, bandwidth, and quality-of-service requirements. Key responsibilities include micro-architecture and design tasks such as RTL design, synthesis, and timing analysis using innovative CAD tools and latest process technologies. Candidates must demonstrate proficiency in Verilog or VHDL and scripting languages like PERL. Preferred experience includes high-speed coherent interconnects, protocol bridges, hardware-managed coherency, system level caches, multiple clock domains, asynchronous interfaces, and industry specifications like CHI, CXL, and PCI-E to solve intricate hardware communication problems.

What does a ASIC Design Engineer earn in California?

Median $214000 from 53 postings across 7 companies.

See salary data

Skills

ASIC Design RTL Design Verilog VHDL Synthesis Timing Analysis CHI CXL PCI-E PERL CAD Tools Hardware-managed Coherency System Level Caches Protocol Bridges Asynchronous Interfaces

What you'll do

  • Deliver world-class memory subsystem solutions by collaborating with architecture and verification teams.
  • Design micro-architecture and RTL for complex SOC interconnects and memory accelerators.
  • Perform synthesis and timing analysis using innovative CAD tools and latest process technologies.
  • Manage complex area, latency, power, bandwidth, and quality-of-service requirements.
  • Implement high-speed coherent interconnects, protocol bridges, and hardware-managed coherency.
  • Develop designs for multiple clock domains and asynchronous interfaces.
  • Apply knowledge of industry specifications such as CHI, CXL, and PCI-E.

What we're looking for

  • BS or MS in Electrical Engineering, Computer Engineering, or a related degree (or equivalent experience).
  • 5+ years of experience.
  • Strong proficiency in Verilog or VHDL.
  • Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency, and system-level caches (preferred).
  • Experience with multiple clock domains and asynchronous interfaces (preferred).
  • Knowledge of industry specifications like CHI/CXL/PCI-E (preferred).
  • Proficiency in a scripting language like PERL.

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