ASIC Design Verification Engineer

Cisco

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$155,000–$222,600 / yr
Employment
Full-time
Posted
11 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $190k
This role $189k
$136k $235k
below market most similar roles pay here above market

This role pays more than 55% of similar roles. Most pay $162,000–$217,525 — the blue band above. At the midpoint, this role pays about $189k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

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The ASIC Design Verification Engineer joins the Common Hardware Group to develop revolutionary data center solutions. In this role, you will architect and maintain block, cluster, and top-level Design Verification infrastructure while building scalable test benches from scratch. You will create and execute comprehensive test plans using constraint-random and directed stimulus to ensure robust verification coverage for complex chips. Key responsibilities include qualifying RTL designs through Gate Level Simulations, debugging issues during post-silicon bring-up, and supporting design testing in emulation environments. You must possess expertise in System Verilog and UVM methodology, along with scripting skills in Perl and Python. The role requires domain knowledge in protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP to solve hardware integration problems for switching, routing, and wireless products.

Skills

System Verilog UVM Python Perl ASIC Gate Level Simulation Veloce Palladium Zebu HAPS P4 PCIe CXL Ethernet RDMA DDR TCP Formal Verification

What you'll do

  • Architect, develop, and maintain block, cluster, and top-level Design Verification environment infrastructure.
  • Build Design Verification environments from scratch for block and cluster levels.
  • Develop and enhance test plans using both constraint-random and directed stimulus.
  • Implement and review code and functional coverage to ensure comprehensive verification.
  • Qualify RTL design by running Gate Level Simulations on netlists.
  • Debug issues during post-silicon bring-up and integration with designers and software teams.
  • Support design testing within emulation environments.

What we're looking for

  • Must have a Bachelor's degree plus 5 years of ASIC experience, a Master's degree plus 3 years, or a PhD.
  • Must have experience in SystemVerilog and UVM methodology.
  • Must have hands-on experience building reusable and scalable test benches from scratch.
  • Must have experience with scripting using Perl and/or Python.
  • Experience with forwarding logic, parsers, or P4 (preferred).
  • Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS (preferred).
  • Knowledge of formal verification tools such as IEV or VC Formal (preferred).
  • Domain knowledge in protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP (preferred).

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